New trends drive ATE open architecture.(automated test equipment)

Semiconductor International, July, 2005 by Furukawa, Yasuo; Rajsuman, Rochit

In the nanometer era, new Semiconductor manufacturing processes, such as copper interconnects, high-k gate dielectrics and low-k passivation, have become necessary. These processes, in tandem with optical proximity correction in nanoscale geometries, are creating an increasing number of new failure modes. In the past, the major failure modes were shorts and opens during the manufacturing process, or wear-and-tear failures; the pass/fail results were easy to judge according to simple logic 1/0 criteria. New failure modes, however, cause variations in delay, crosstalk among signals, spurious transients, and many other faults that are sometimes hard to define. Such failure modes require engineering judgment criteria to reflect the variables in the manufacturing process,...

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