Cleaning's role in high-k/metal gate success.
Semiconductor International, February, 2006 by Barnett, Joel; Moumen, Naim; Peterson, Jeff J.; Hussain, Muhammad Mustafa; Song, Seung-Chul; Bersuker, Gennadi
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The International Technology Roadmap for Semiconductors (ITRS) projects that future high-performance processes will require transistor gate stacks to have an equivalent oxide thickness (EOT) of <1.0 nm for the 45 nm node. (1) As EOTs scale to <2 nm, the polysilicon gate depletion becomes a significant problem, and metal electrodes, whose depletion regions are almost nonexistent, become necessary.
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Importantly, when the EOT is scaled this drastically, the bottom interface quality has a significant impact on device performance. Additionally, the integration of high-k and two ...
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