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Industry: Email Alert RSS FeedFuturebus+ logical spec shows at Buscon. (The logical specification for the Futurebus+ multimaster scalable bus architecture) (contains related articles on introduction of SPARC boards at ) (product announcement)
EDN, February, 1990 by Coco, Donna
Futurebus logical spec shows at Buscon National, Signetics confirm work on new chip sets LONG BEACH, CA--The logical specification for Futurebus --the multimaster, scalable bus architecture that extends the original Futurebus to 256 bits and 1 Gbyte/sec--will be released next Wednesday during Buscon here.
Also at the show will be initial details of a National Semiconductor Futurebus chip set that will include an arbitration controller and four backplane-transceiver-logic (BTL) chips, plus announcements of the silicon intentions of Signetics Corp. Also officially released at the show will be the bridge specifications to get VME and Multibus systems talking to Futurebus boxes. The details of the bridges were worked out in meetings after Buscon...
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