Synchronous cache RAMs run at 50 MHz. (random access memory)(Cypress Semiconductor Corp.'s CY7B173 and CY7B174 semiconductor memory) (Hardware Review) (Evaluation)

EDN, January, 1992 by Quinnell, Richard A.

The CY7B173 and CY7B174 synchronous cache RAMs operate at 50 MHz, but they offer more than just high speed. To simplify cache-memory subsystem design, the devices incorporate logic functions such as address latches and burst counters.

Both memories are organized as 32k x 9 bits. They operate synchronously, sampling the address, data, and control lines on the rising edge of the clock input signal. The clock's minimum cycle time is 20 nsec, allowing operation at 50 MHz. Only the output-enable line operates asynchronously, setting the data output lines to high impedance within 7 nsec of de-assertion.

For the memories to respond to a given clock cycle, both the chip select and address-strobe lines must be properly asserted. The devices have two...

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