$179 buys a single-chip, 50-MHz desktop SPARC CPU. (Texas Instruments introduces MicroSPARC) (Product Announcement)

EDN, November, 1992 by Weiss, Ray

Next-generation, 32-bit SPARC RISC is more than just high-throughput, superscalar SuperSPARCs or hyperSPARCs or hyperSPARCs (EDN, June 4, 1992, pgs 89 to 94). It also includes high-integration, minimal SPARC [mu]Ps that target mid- to low-end computing. Texas Instruments' MicroSPARC is the first of these integrated SPARCs. Running at 50 MHz, with two on-chip caches, it delivers first-generation execution speeds (see table).

MicroSPARC represents a new direction in SPARC design, which has been growing in complexity and size. Unlike the current generation of desktop SPARCs, the MicroSPARC targets low-chip-count designs. It integrates a dynamic-RAM (DRAM) refresh and addressing controller and a 5-slot SBus controller on chip. You can cobble together a...

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