Superscalar SPARC executes as many as three instructions in parallel. (Texas Instruments' SuperSPARC microprocessor) (Wescon/92 supplement) (Product Announcement)

EDN, November, 1992 by Weiss, Ray

The Texas Instruments' third-generation RISC microprocessors ([mu]Ps) are the first superscalar implementation of the SPARC RISC (reduced-instruction-set-computer) processor. SuperSPARC has a 3.1M transistor chip (0.8-[mu] BiCMOS) with 36 kbytes of internal cache. The processor can execute as many as three instructions in parallel each clock cycle.

SuperSPARC's development is the result of a joint Sun and TI project. The first chips will chug along at 40 and 45 MHz, with later versions hitting 50 MHz--and eventually 100 MHz. A simulated SuperSPARC at 40 MHz delivers 42.9 SPECmarks (40 SPECint and 45 SPECfp), which is the equivalent of 42.9 VAX-MIPS (a VAX 11/780 is considered a 1-MIPS machine). SPEC benchmark programs run on the target CPU and compare to...

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