Superscalar SPARC RISC integrates CPUs, cache controller, and SRAM. (central processing unit) (Cypress Semiconductor introduces CY7C620 multichip module) (Wescon/92 Supplement) (Product Announcement)

EDN, November, 1992 by Weiss, Ray

Single-chip implementations are not the only form for a super-scalar RISC SPARC microprocessor ([mu]P). Cypress Semiconductor's approach is a multichip module that tightly integrates a CPU chip with a cache controller and fast static-RAM (SRAM) memory. Running at 66.7 MHz, the CY7C620 processor chip issues as many as two instructions per clock cycle. It features an 8-kbyte local instruction cache, supplemented with as much as 256 kbytes of zero-wait-state RAM.

The hyperSPARC chip set--the CY7C620 CPU, CY7C625 cache controller, and CY7C627 SRAM--fits on a SPARC Level 2 MBus module. This module drops right into the Sun SPARCstation 10 or SPARCserver 10 boxes, or other Sun servers. Unlike the TI SuperSPARC module, which holds one CPU, Cypress modules...

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