ASIC design/verification environment. (Electronic Design Automation).(Aldec Riviera-Elite)(Brief Article)(Product Announcement)

EDN, August, 2002

* Teams Summit Design's Visual Elite design environment with Aldec's Riviera simulator to provide a complete HDL design-entry and -verification environment * Supports both graphical and textual VHDL, Verilog, C/ C , SystemC, and mixed-language design, while automatically generating optimized HDL code for leading logic and behavioral-synthesis tools * Riviera-Elite, from $20,000 Aldec Inc, 1-702-990-4400, www.aldec.com No.

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