Software tool makes short work of polyglot IP in SOC ICs.(Leading edge: what's hot in the design community)

EDN, August, 2003 by Strassberg, Dan

EEs WHO DESIGN TESTABILITY FEATURES into SOC (system-on-chip) ICs and those who design verification and production-test programs for such devices have to regard Agilent's SmarTest PG (program generator) CTL (core-test language) Browser as a work in progress. Nevertheless, even without the ability to provide waveform displays of test patterns and expected and actual device responses, the software tool can be a huge help to designers of ICs that integrate multiple IP (intellectual-properly) cores. Such chips often use cores from several IP vendors, and, to develop the cores, different IP vendors commonly use different tool sets. This situation forces SOC designers to simultaneously work with as many as a dozen software tools. Although at least a year may pass before...

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