Digital timing chip for OC-3 line cards.(Telecom, Datacom & Voice ICs)

ECN-Electronic Component News, November, 2003

Zarlink Semiconductor has expanded its portforlio of timing devices for optical networking equipment with the ZLTM30410 digital PLL (phase-locked loop), a full-featured timing chip with what is said to be the industry's lowest jitter, for access line cards operating at OC-3 (Optical Carrier level 3) rates. The chip generates and synchronizes clock signals used by other line card devices such as OC-3/STM-1 (synchronous transport module level 1) framers, mappers, switches and optical line interface chips. The company's analog PLLs connect seamlessly to the ZL30410 and support higher-speed applications by producing clock signals for OC-12/STM-4 or OC-48/STM-16 framers. The device's jitter performance is said to be 30 percent lower than comparable digital PLLs. Jitter, a...

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