Synopsys Design Compiler Topographical Technology Adopted by IBM to Accelerate ASIC Designs for Customers.
PR Newswire Europe, May, 2007
MOUNTAIN VIEW, California, May 7 /PRNewswire/ --
- 5% Correlation Between Synthesis and Layout Key to Predictable ASIC Design Flow
Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that IBM has added support for topographical technology in its 90-nanometer (nm) and 65nm-based application-specific integrated circuit (ASIC) design kits. Synopsys' Design Compiler(R) topographical technology enables IBM's ASIC customers to achieve tighter correlation between design results such as timing and power seen during synthesis and the results achieved after layout. This eliminates the need for time-consuming iterations between synthesis and layout to achieve design closure, thus significantly accelerating overall...
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