Motorola and Lucent Technologies Demonstrate Highest Performance DSP Core, On Schedule From the StarCore Joint Design Center - Product Announcement

Cambridge Telcom Report, Dec 13, 1999

Lucent Technologies Microelectronics Group and Motorola Monday announced the availability of a jointly-developed digital signal processor (DSP) architecture that can reduce the time to develop communications electronic products by approximately 50 percent. The StarCore SC140 DSP core delivered Monday in initial silicon has "DSP performance superior to anything else shipping in the industry," according to Will Strauss, president of market research firm Forward Concepts (Tempe, Ariz.).

"For a DSP core to set a single new standard -- in ease of development, performance, power consumption, or compact application code size -- is exceptional," said Jim Boddie, executive director of the StarCore Joint Design Center. "But to raise the bar and deliver in all four of these areas simultaneously has been unheard of until now." A key technology enabling these benefits is the StarCore SC140 compiler, which is a system-level tool for translating DSP design ideas into high-performance DSP products.

"The race in the DSP arena has traditionally centered on processing speeds, power consumption, and code sizes," Boddie added. "Now the technology battleground is expanding to encompass DSP compiler technology, because of its direct link to product delivery schedules. This breakthrough SC140 compiler capability enables tangible, bottom-line benefits."

The architecture and related software development platform are expected to be made available from Lucent and Motorola for their respective customers in December 1999. Lucent and Motorola plan to release products in high volumes based on the StarCore SC140 DSP early next year. The companies have collaborated on the StarCore SC140 DSP core through their StarCore Joint Design Center, a cooperative research and development initiative created to define next-generation DSP cores and development tools. The StarCore SC140 core is the first implementation of the StarCore SC100 generation of DSP cores from the two companies. SC140 documentation and training courses are available now.

The StarCore SC140's efficient variable-length execution set (VLES) architecture model is the first to realize the compilability and high performance potential of a multiple issue advanced DSP architecture, with the low power consumption and compact code density demanded by the applications of today and tomorrow. VLES is a multi-issue architecture that allows up to six executable 16-bit RISC instructions, and two prefix instructions to be issued simultaneously with no alignment restrictions or space wasting NOP (No Operation) padding; which efficiently takes full advantage of the core's 16 functional units.

Designers of next-generation communications equipment will want to leverage the advantage provided by the StarCore SC140 to build more capable products with faster data rates, enhanced end user features, and infrastructure equipment that handles more channels for less development and silicon cost than ever before. This new core is designed to drive the development of high-performance telecommunications applications such as next- generation (2.5 and 3G) wireless handsets and base stations, digital subscriber line (DSL) client and central office equipment, and voice over IP telephony applications. The SC140 will also be a great fit for enabling true universal access (voice, data, ISDN, etc) head-end equipment, and connected PDAs.

Addressing Top Four Market Needs The StarCore SC140 is the first DSP core to deliver on the top four market needs for next-generation DSP applications:

-- Efficient Compilability: Faster time-to-market to meet customer demandfor new applications by allowing an unprecedented 90 percent of thesoftware code development in C/C , while still obtaining the highperformance, low power dissipation, and compact code density typicallyassociated with programming in the device's native assembly language.

-- Leadership Performance: Enabling next-generation, compute-intensivecommunication applications with 1200 MMACS/3000 RISC MIPS at 300 MHz.

-- Low Power per Function: Lowest power-performance ratio at 0.11ma/MMAC(198 mW total) at 1.5V. Ultra low power with 0.066mA/MMAC (28mW total)at 0.9V. Ideal for new 2.5 and 3G wireless handsets, which requireimprovement on current drain with much greater performance.

-- Better Code Density: Requires less memory for a given application, and therefore reduces system cost on the order of 50%.

Industry Analysts Back StarCore SC140 According to Will Strauss, "Motorola and Lucent have put their A-Teams in the StarCore design center. StarCore has a well-planned roadmap beyond the StarCore SC140, and the future looks very good for the center."

Jack Quinn, president of Micrologic Research stated, "StarCore is hitting the market at the right time with this impressive DSP core technology. I have not seen anyone else out there with a DSP core to address third-generation wireless handsets and infrastructure. StarCore's combination of high- performance and low power is exactly what is needed for third-generation cellular phones. Overall, StarCore is a very impressive endeavor."