PMC-Sierra Introduces New OC-48 Chip Set Architecture to Enable Next Generation Optical Network Deployment - Product Announcement

Cambridge Telcom Report, May 1, 2000

PMC-Sierra (Nasdaq:PMCS) Monday announced a new OC-48/OC-48c (2.5 Gbit/s) channelized architecture designed to completely revolutionize the way carrier and Internet Service Provider (ISP) networks are built, deployed and managed.

The CHESS (Channelizer Engine for SONET/SDH) chip set will allow for convergence of traditionally separate voice and data infrastructure into new, highly integrated carrier-class multi-service networks. The CHESS chip set is the industry's first and only chip set architecture allowing IP Routing, ATM/Frame Relay Switching, SONET/SDH digital cross connect/add-drop multiplexing and Dense Wavelength Division Multiplexing (DWDM) transport functionality to be built in a single, space-efficient hardware platform.

By replacing as many as five or six older, discrete network equipment elements, multi-service equipment networks utilizing the CHESS chip set will enable carriers and ISPs to provision a greater number of services more dynamically and at lower cost than ever before (see Figure 1). The CHESS chip set manages scarce SONET/SDH bandwidth and DWDM lambda wavelengths which are critical to the effective deployment and operation of true multi-service networks realizing "Any-Service, Any-User, Any-Channel". These networks can now utilize simplified software management layers making them significantly easier for carriers and ISPs to operate.

The CHESS Chip Set Upgrades MANs and Edge WANs Which Are Critical to Carrier Business Growth Carriers are urgently upgrading their infrastructure in emerging, high-growth Metropolitan Area Network (MAN) and edge Wide Area Network (WAN) regions to maintain and grow a very lucrative Service Level Agreement (SLA) provisioning business. These networks are ideally suited for SONET/SDH fiber backbones due to its scalability, availability and reliability. They are, however, highly under-utilized with the current OC-3/STM-1 (155 Mbit/s) and OC-12/STM-4 (622 Mbit/s) rate operation. The availability of the CHESS chip set provides an immediate upgrade path to OC-48/OC-48c/STM-16 (2.5 Gbit/s) rate operation. The CHESS chip set can also scale beyond 2.5 Gbit/s rate applications to support future OC-192/STM-64 applications running at 10Gbit/s rates.

The CHESS Chip Set Creates Next Generation, Carrier-Class, Multi-Service and Optical Equipment The edge of the network is a very challenging environment for a carrier or ISP to manage. MAN and edge WAN networks must not only aggregate the multi-protocol, low- and multi-rate DS0 (64 Kbit/s) to DS3 (45 Mbit/s) traffic from access customer premise regions, but are now also required to aggregate the wavelength lambda base rate of OC-48/OC-48c (2.5 Gbit/s) traffic from native DWDM transport networks. To meet these difficult requirements it is necessary to manage and groom SONET/SDH traffic at both STS-1/DS3 (51/45 Mbit/s) base access rate and at OC-48/STM-16 (2.5 Gbit/s) base DWDM rate granularities. The CHESS chip set is the first and only industry chip set to provide capability for such dual-rate SONET/SDH grooming capability.

The CHESS chip set provides SONET/SDH framing capability at each of the key OC-3, OC-12 and OC-48 optical line rates. Its STS-1 channelized traffic grooming capability allows for the development of dedicated service processing cards such as Packet-over-SONET, ATM and Frame Relay that replace entire, dedicated network service equipment utilized previously (see Figure 2 and Figure 3). But perhaps most importantly, the STS-1 grooming capability of the CHESS chip set will allow for sub-lambda wavelength processing such that multiple user services can be run over individual 2.5 Gbit/s lambda wavelengths (see Figure 4). This solves the optimal lambda utilization problem of provisioning more than a single user service per lambda and will help enable the creation of new multi-service optical equipment classes such as the integration of cross connects, add-drop multiplexers and switches.

"As the initial offering in our OC-48 strategy, the CHESS chip set architecture unveiling is a highly anticipated event for PMC-Sierra," said Steve Perna, PMC-Sierra's vice president and general manager, Optical Networking Division. "In conjunction with our key strategic customers, we have focused over the last 15 months on developing an OC-48 Internet Service Provider architecture that leverages significant system level expertise designed to optimize the scarce resources of network bandwidth, lambda wavelength and equipment form factor. The CHESS chip set architecture will significantly improve the ability of our customers to provide increased service level provisioning in their next-generation carrier-class equipment," he concluded.

Pricing, Packaging and Customer Support The CHESS chip set architecture consists of five devices, each by itself unique in the industry for its high density and functionality, designed to operate seamlessly together (See Table 1).

-- SPECTRA-2488: OC-48/OC-48c/STM-16 and 4xOC-12/STM-4 SONET/SDH framer with STS-1/AU3 channelizer