Serial ATA: a comparison with Ultra ATA technology - Serial ATA

Computer Technology Review, Nov, 2002 by Rob Cavin

In past years, increasing hard disk transfer rates have forced the ATA interface specification to be continuously updated to avoid becoming the limiting factor in disk 110 performance. As consumers embrace new usage models such as digital video creation and editing, digital audio storage and playback, file sharing over high-speed networks, and other data-intensive applications, demands on hard drive throughput are expected to increase even further. To keep pace, the storage interconnect must be developed beyond existing Ultra ATA technology. The new approach is Serial ATA, a serial implementation of the parallel Ultra ATA interface. With this paradigm shift in I/O design, the roadmap of ATA will be extended beyond the theoretical limits of the Ultra ATA bus.

We'll explore the technical differences between Ultra ATA and Serial ATA technology, and to provide explanation for the transition from a parallel to serial bus architecture. The key design points of each technology will be described and compared, followed by an overview of the system level and end-user advantages of Serial ATA technology. The ATA protocol itself will not be discussed, as in this sense there is no difference between the technologies.

Serial ATA is software-compatible with the ATA interface and thus will appear to the OS as a standard ATA device. Note that it is assumed the reader has an understanding of electrical engineering design principles; the paper is intended primarily for OEMs, system designers, and product manufacturers who are considering adding Serial ATA capability to their designs.

Technology Introduction

Ultra ATA is the primary internal storage interconnect for the desktop, connecting the host system to peripherals such as hard drives, optical drives, and removable magnetic media devices. Ultra ATA is an extension of the original parallel ATA interface introduced in the mid 1980s and maintains backward compatibility with all previous versions of this technology. The latest revision of the Ultra ATA specification accepted by the ANSI supported INCITS T13 committee, the governing body for ATA specifications, is ATA/ATAPI-6, which supports up to 100MB/sec data transfers.

Development of the ATA/ATAPI-7 specification, an update of the parallel bus architecture that provides up to 133MB/sec, is currently being finalized (see www.t13.org).

Serial ATA is the next -generation internal storage interconnect designed to replace Ultra ATA technology. Serial ATA is the proactive evolution of the ATA interface from a parallel bus to a serial bus architecture. This architecture overcomes the electrical constraints that are increasing the difficulty of continued speed enhancements for the classic parallel ATA bus. Serial ATA will be introduced at 150MB/sec. with a roadmap already planned to 600MB/sec, supporting up to 10 years of storage evolution based on historical trends. Though Serial ATA will not be able to directly interface with legacy Ultra ATA hardware, it is fully compliant with the ATA protocol and thus is software compatible (see www.serialATA.org).

OVERVIEW OF PARALLEL VS. SERIAL BUS ARCHITECTURE: Ultra ATA Bus Architecture

Bus Design: The latest revision of the ATA specification, ATA/ATAPI-6 where Ultra ATA 100 is defined, maintains backward compatibility with all previous ATA revisions, using the standard 16-bit, wide, parallel data bus and 16 control signals across a 40-pin connector.

Bandwidth: To understand the 100MB/sec throughput, several factors must be considered. With a 16-bit data bus, two bytes are transmitted per bus transaction. Thus to achieve a throughput of 100MB/sec, the data bus must be clocked at 50MHz. To minimize strobe design complexity, Ultra ATA uses a double data rate or double-edge clocking mechanism for all Ultra DMA transfers. Using this technology, data is registered both on the rising and falling edges of the data strobe, halving the required strobe frequency. Thus the bandwidth is: 25MHz strobe, multiplied by 2 for double data rate clocking, then multiplied by 16 bits per edge, then divided by 8 bits per byte, which equals 100MB/sec.

Timing: As mentioned above, data must be clocked at 50MHz, or every 20ns. Note that because of data setup and hold times, all data lines must in fact switch and settle within approximately 10ns (see Figure 1). It is this worst-case switching time that designers must meet.

Serial ATA Bus Architecture

Bus Design: In contrast to Ultra ATA's parallel bus design, Serial ATA uses a single signal path to transmit data serially, or bit by bit, and a second serial path to return receipt acknowledgements to the sender. Because each of these signal paths is a two-wire differential pair, the Serial ATA bus consists of four signal lines per channel. Control information is transmitted either as short predefined bit sequences that are distinguishable from data, in packet format, or using out-of-band signaling (control signals sent using on/off signal pulses, similar to Morse code), and thus does not require separate transmission lines.