SDRAM Memory: DRAM And Beyond - Industry Trend or Event

Computer Technology Review, August, 1999 by Stuart Atkins

Between now and the year 2000, a broad spectrum of complex and high-speed memory architectures will enter the PC landscape. Currently, PC main memory is transitioning from EDO (Extended Data Out) memory to SDRAM (66MHz and 100MHz) with Synchronous DRAM expected to dominate the market during 1999 and the first half of 2000. At least four technologies are evolving from approximately 1998 to the year 2000: SDRAM, SDRAM II (DDR), SLDRAM (SyncLink), and Rambus. Table 1 is an approximate time-line regarding the emergence of future memory technologies.

Predicting where the "DRAM dust" will settle is difficult. All of the top ten DRAM manufacturers such as Samsung, Toshiba, and Hitachi are developing Rambus, yet also continuing aggressive R&D related to alternative next-generation DRAM technologies such as DDR. We thus find an intriguing blend of both partners and competitors working together. Nevertheless, and in spite of the unknowns, a general overview and explanation of where SDRAM and other future technologies may head will serve to give us a better grasp of key issues. In a market where change is the only constant, our goal is understanding rather than certainty.

To briefly cover subjects related to next generation memory, we will first explore factors driving the thirst for bandwidth within the PC industry. Second, definitions of each of the six memory technologies will assist us in comparing and contrasting the differences between these various technologies. And last, some thoughts on how Kingston fits into the overall industry evolution between now, the year 2000, and beyond.

BANDWIDTH AND THE "PERFORMANCE GAP"

Rapid advancements in both hardware and software are now emerging to meet acute performance needs within the PC industry. In fact, a number of years ago, Gordon Moore, the president and cofounder of Intel, predicted that CPU performance would double every 18 months (known as "Moore's Law"). Moore was right. From 1980 until now, the standard operating frequency of Intel and other microprocessors has increased roughly 100 times (5MHz to 500MHz). However, over the same time period the standard operating frequency of "page mode" DRAM memory has increased by roughly five times. Even newer Fast Page Mode, EDO, and SDRAM have only increased performance by roughly 15 times. There is a clear "Performance Gap" between processors and memory.

In the past, as microprocessors benefited from architectural and manufacturing enhancements, important enhancements for DRAMs have usually occurred in manufacturing. The density (storage capacity) of DRAMs has increased from roughly 1Kbit (thousand bits) to 64 - 128 Mbits (million bits) per chip. This in turn has reduced the number of DRAMs needed for memory, yet the design improvements required to accelerate DRAM data transfer rates have not kept pace. In short, transfer rates have not kept pace with density increases.

As for advancing software demands, the entrance of memory-intensive multimedia applications for both business and consumers is increasing the thirst for bandwidth. With advances in microprocessor frequency, in addition to software and design changes that shift multimedia processing to memory subsystems, PC main memory requirements could soon exceed 1GB (billion bytes). Furthermore, as advanced operating systems such as OS/2 and Windows NT become more complex, memory requirements will also rise to meet performance and feature demands.

In an attempt to address this performance gap, technology manufacturers have utilized various innovations. SRAMs (Static RAMs) were used to develop caches, which were helpful for various information processing applications, yet fell short when it came to graphic-intensive, multimedia applications. In addition, attempts were also made to widen the system bus that is used to pass data between the processor and DRAMs. As these buses are widened, signal integrity and timing become critical aspects of data transmission. The margin for error thus decreased given the wider bus, yet this further increased the need for more advanced and exacting memory technology.

Consequently, the need arises for new memory technologies that can deliver the required band-width. In addition to SDRAM, four other evolutionary memory technologies occupy the bandwidth landscape: SDRAM, VCM, DDR, SLDRAM, RDRAM, Concurrent RDRAM, and Direct RDRAM. A brief overview and definition of next- generation memory will serve to assist in both the understanding and future application of these emerging technologies.

SIX PLAYERS IN THE NEXT-GENERATION LANDSCAPE

DEFINITIONS

SDRAM

Synchronous DRAM (SDRAM) is "in synch" or synchronized to the system clock that controls the CPU. The clock that controls the microprocessor also controls the SDRAM, thus eliminating wait states and reducing data retrieval times. This synchronization allows the memory controller to know on which clock cycle data requests will be available. Data is thus input to the rising edge of the clock instead of with every two clock cycles (like EDO) or every three clock cycles (like FPM). SDRAM also utilizes multiple memory banks that function simultaneously, in addition to a burst mode feature that addresses an entire block rather than just one piece of data. SDRAM is currently in production.