Mako PCI bus chipset to be uncaged by Toshiba at Comdex

Business Wire, Nov 7, 1994

SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 7, 1994--Toshiba America Electronic Components Inc. (TAEC) Monday announced that it will introduce the Mako PCI chipset, a R4x00 series compatible PCI bus chipset, at Fall Comdex '94.

Toshiba's Mako chipset provides system designers with a cost-effective, easy means of designing MIPS-based systems in the embedded, PC or workstation environments.

According to Jeanclaude Toma, director of marketing for Toshiba's RISC/CPU products, the Mako chipset is a three-chip solution consisting of an Address Control Chip (ACC) and two identical Data Path Control chips (DPC). "Mako complements Toshiba's R4x00 family of RISC processors as part of a total RISC system solution in embedded applications and high-end personal computer systems," he stated.

Toma added, "The PCI standard has been widely accepted in the industry by both PC and embedded systems designers." In fact, embedded applications such as VME boards use the PCI Mezzanine Cards (PMC) standard recently adopted by the IEEE.

The Mako chipset features built-in memory controllers for both main memory and Level 2 cache in write-back and write-through modes. The Mako chipset is fully compatible with the R4600(tm), R4400(tm)SC, R4400PC and R4200(tm) microprocessors in big endian or little endian modes. Additional features include asynchronous PCI bus operation up to 67 megahertz, four PCI masters, one to eight banks of dynamic random access memory (DRAM) with a maximum of 256 megabytes (MB), and up to 1MB of second level cache.

"The Mako PCI chipset makes upgrading current PCs easy by providing a modular system architecture that allows integration of the latest processors, compatible input/output (I/O) interfaces and memory systems" Toma continued. "It provides users with the versatile, high-performance control logic needed to support a wide range of RISC-based PC applications."

Mako supports applications whose graphics functions are provided via a PCI bus supported graphics controller and whose memory requirements are met by standard DRAM. A typical Mako/PC system includes a R4x00-based motherboard, PCI and EISA or ISA add-in cards.

The chipset is designed in a dual voltage technology. The processor and cache operate at 3.3 volts (V) and the main memory and PCI bus interfaces operate at 5.0V. This mixed-voltage capability provides the flexibility needed for today's emerging low-power designs.

Mako converts R4x00 system interface signals (SYSAD) to a 32-bit PCI. This local bus can interface directly to other chipsets that support many industry standard buses, including ISA, EISA, SCSI and other popular I/O buses such as VME.

Each device is packaged in a 208-pin quad flat package. Samples will be available first quarter, 1995, with full production expected to begin at the end of the quarter. Pricing in 1,000 piece quantities will be approximately $75 per chipset.

Mako joins Toshiba's growing line of MIPS RISC-compliant chipsets including the mixed-voltage Tigershark(tm) chipset, the first to provide local bus signal translation between all R4x00 RISC family processors and an Intel i486(tm) bus.

TAEC is the North American manufacturing, sales and marketing arm of one of the world's largest suppliers of semiconductors, integrated circuits and electronic components for industrial and consumer applications. The company is the recognized leader in CMOS technology and has one of the broadest IC product lines in the industry. In addition Toshiba is a leading manufacturer of technologically advanced electron tubes and solid state devices, including color picture tubes, display monitor tubes, liquid crystal displays, medical tubes, rechargeable lithium ion batteries, microwave components, laser diodes and optical transmission devices.

Toshiba's RISC facility is located at 1060 Rincon Circle, San Jose, Calif., 95131.

Example Mako System

A typical Mako system uses a graphics controller connected to the PCI bus and DRAM for the system memory module. The motherboard typically includes the following:

-- An R4xxx series microprocessor that includes two first level caches. Some versions may have built-in control and data paths for a second level cache, in which case, the ACC's cache controller is disabled.

-- Level 2 cache controlled by the ACC is implemented with fast, conventional, static SRAMs.

-- A Mako ACC and two Mako DPCs that provide all the necessary control interface functions between the processor, Level 2 cache, system memory, and PCI bus.

-- System Memory is typically packaged in Single-In-line Memory Modules (SIMMs) for expansion, configuration flexibility, and handling convenience. It includes system memory arrays, array drivers, and a small amount of associated logic. A maximum of eight banks (eight RAS signals) of system memory are allowed. Each bank of system memory is 72 bits wide.

-- Interfaces for :

Memory (DRAM)

External (PCI) I/O buses

-- Clock Generator

It may also include:

-- Configuration PROM used by the R4xxx processor (optional)