Fujitsu HaL develop next generation 64-bit RISC processor; SPARC 64 is first implementation of SPARC V9 architecture

Business Wire, Feb 15, 1995

CAMPBELL, Calif.--(BUSINESS WIRE)--Feb. 15, 1995--Fujitsu Ltd. and its Campbell, California-based affiliate HaL Computer Systems Inc. have developed a RISC processor that is the industry's first implementation of the SPARC V9 64-bit instruction set architecture.

The development is being announced today at the IEEE International Solid-State Circuit Conference (ISSCC) in San Francisco.

Called SPARC 64, the processor is a multi-chip module (MCM) containing seven chips -- a CPU, four cache memory chips (64kbytes each), a memory management unit (MMU), and a clock chip -- which are mounted on a 6.13cm x 4.46cm ceramic board. The chips are fabricated using Fujitsu's twin-well, 3.3V, 0.4-micron CMOS process with four layers of metalization. There are approximately 22 million transistors in total, and the effective channel length of transistors is 0.35 micron.

SPARC 64 tracks 64 outstanding instructions, and utilizes register renaming and dataflow execution to achieve an estimated integer performance exceeding 256 SPECint92 and floating point performance greater than 330 SPECfp92 at 154MHz. Moreover, unlike existing microprocessors, all memory, beginning with the cache memory, features built-in error correction and detection functionality, thereby offering reliability on par with existing large-scale computer systems.

"We're extremely proud and excited about our engineering effort for SPARC 64," commented Arthur G. Goldberg, HaL's executive vice president. "We believe this establishes the basis for the highly competitive products that we will be introducing." -0-

Note: SPARC V9 is a trademark of SPARC International and refers to the 64-bit architecture developed by Fujitsu, Sun Microsystems and others.

CONTACT: HaL Computer Systems Inc.

Clark Hoyle, 408/379-7000, ext. 1391