Cypress Introduces First PC Chipset with On-Board Cache; Pentium-Class Chipset Offers Peak Performance and Lowers PC System Costs

Business Wire, June 13, 1995

SAN JOSE, Calif.--(BUSINESS WIRE)--June 13, 1995--Cypress Semiconductor Corporation today introduced the hyperCache(TM) Chipset for Pentium(TM)-class personal computers, the industry's first PC core logic chipset with integrated second-level cache. The new approach to PC chipset architecture improves system performance while offering savings in cost, board space, and power usage.

The hyperCache Chipset, in addition to providing integrated high-performance second-level cache and cache tag, offers a variety of functions to ease the PC design process. It includes a DRAM controller that supports both Fast Page Mode and Extended Data Out (EDO) DRAMs. The hyperCache Chipset also integrates key peripherals, including local bus IDE with master mode, keyboard and mouse control, DMA interrupt control, and real-time clock with extra CMOS RAM. Support for both the PCI and ISA busses is also incorporated in the new chipset.

Cypress first entered the PC chipset market with the 1994 acquisition of Contaq Microsystems. Contaq, which designed the first i486 chipset to offer a PCI to ISA bridge, has developed a strong customer base internationally. Cypress is engaged in strategic relationships with PC manufacturers worldwide as a leading supplier of cache memory (static RAMs and modules) and clock synthesis products. These include such companies as AST Research, Compaq, Hewlett-Packard, IBM, and Olivetti.

Cypress President and CEO T.J. Rodgers stated, "Cypress is a natural to design and develop the first Pentium chipset with cache memory, the next step in the evolution of the personal computer. No other vendor has Cypress's depth of expertise in SRAM cache memory, high-speed logic, clock generation, and core logic design. These factors, combined with our manufacturing strength, allow us to offer our customers a winning solution."

Dan McCranie, Cypress's vice-president of marketing and sales, said, "Today second-level cache is a standard feature in high-performance PCs. The strong PC market has increased cache SRAM demand, resulting in tight supply for this product. By incorporating our high-performance cache directly on the chipset, Cypress has improved system performance while providing a guaranteed supply of cache for PC manufacturers. We anticipate the innovative hyperCache Chipset to become a standard with the leading PC companies worldwide."

Integrated High-Performance Cache

The hyperCache chipset consists of three chips -- the CY82C691 PCI and Memory Controller, the CY82C692 Data Path Chip with integrated cache, and the CY82C693 Peripheral Controller.

The CY82C692, includes 128 Kilobytes (KB) of two-way set associative, synchronous pipelined cache. This cache structure provides a significantly higher level of performance than standard asynchronous caches(1). In fact, the hyperCache Chipset's 128KB cache provides performance equal to or better than 256KB of direct mapped asynchronous cache, and the cache size can be easily upgraded to 1 Megabyte. The combination of the advanced cache structure and time savings gained by eliminating delays associated with going on and getting off external SRAMs allows the hyperCache Chipset to provide 3-1-1-1 performance (the number of clock cycles it takes to read the first cache line, and each of the three succeeding cache lines).

An optional fourth chip in the hyperCache chipset is a 16K by 64 cache RAM -- the CY82C694. It interfaces seamlessly to support large cache sizes up to 1 Megabyte (in 128KB increments).

Third Party Comments

Antonio Macri, Purchasing Director for Olivetti, said "The hyperCache Chipset from Cypress represents an impressive achievement in the first integration of cache RAM into a Pentium chipset. With cache RAM now as a fundamental component in high-performance personal computers, Cypress has made a key contribution in simplifying PC design."

Linley Gwennap, editor of the influential newsletter Microprocessor Report, said, "Cypress's innovative design makes good use of the company's experience in the SRAM market. The integrated cache offers cost and footprint savings while increasing performance due to the synchronous, set-associative design. This combination helps hyperCache stand out from the pack and should give Cypress a quick entry into the high-volume Pentium chipset market."

Full Feature Set

The CY82C691 performs system controller functions, including DRAM control supporting up to 6 banks of DRAMs (768 MB maximum) and shared DRAM support. The CY82C691 also provides cache control up to 1 Megabyte, and CPU and PCI interfacing. In addition, it includes an integrated 8K x 21 cache tag.

The CY82C693 is the I/O controller and integrates peripheral control. It includes a PCI to ISA bridge, integrated enhanced IDE with bus mastering, support for five PCI masters, integrated DMA/Interrupt control, real-time clock, integrated keyboard and mouse control, general-purpose I/Os, and power management. The high degree of integration means that no external transistor-transistor logic (TTL) is required.