ALi Provides New High-Performance System Core Logic Chip Set for Servers and Workstations; Optimized for multi-tasking and multi-processing environments with multi-processor systems using Pentium, K5 and M1 CPUs

Business Wire, May 30, 1995

SAN JOSE, Calif.--(BUSINESS WIRE)--May 30, 1995--Acer Labs Inc. (ALi) today announced a new family of advanced core logic chip sets for servers and high-performance workstations using Pentium, K5 and M1 CPUs.

ALi's GENIE family is the answer to the demands placed on servers and workstations by the new operating environments which are not well served on today's PC architecture when it comes to multi-tasking, multi-threading, multi-processing requirements. The GENIE chip set is ideal for the design of file servers, high-performance multi-processor application servers, and high-performance workstations. Utilizing a MESI cache architecture, integrated ECC and optimized I/O and CPU, GENIE provides very high-performance system design for these demanding applications.

ALI's GENIE 1600 core logic chip set consists of three highly integrated chips using an architecture designed to optimally balance I/O and CPU performance for very high throughput. It features a memory bandwidth of 264 MB/sec. and direct memory addressing to 1 gigabyte. The chip set supports multiple CPUs for versatility and high performance.

Aimed at high-end business server and engineering applications, the GENIE system logic chip set can also by used for a high-performance Windows 95 desktop workstation or a high-performance dual-processor workstation for Windows NT or OS/2. It complements ALi's Aladdin core logic family, aimed at business and home PC applications.

According to Dr. S.J. Lee, ALi vice president of Technology, "This new level of system performance now attainable with GENIE is unsurpassed in the industry, and cannot be achieved by today's shared L2 cache pseudo SMP architectures."

The heart of the new chip set is ALi's 64-bit concurrent bus architecture known as PICA (Performance-enhanced I/O and CPU Architecture), which was originally developed by ALi for use with the MIPS 4x00 RISC processor family. The chip set provides full concurrency between all processors and PCI I/O devices, allowing system throughput to increase linearly as processor performance increases. On-chip ECC provides the required memory protection for high system reliability, which is especially critical in server applications.

The first version of the GENIE chip set family supports the x86 architecture of the Intel Pentium, Advanced Micro Devices K5 and Cyrix M1: -0-

-- M1601 high-performance 64-bit direct-map L2 MESI serial cache controller for x86 multiprocessor systems using separated cache memory

-- M1609 general-purpose memory and multi-channel I/O controller which incorporates a 64-bit memory bus controller and 32-bit PCI I/O bus

-- M1513 standard PCI-ISA bus controller with APIC -0-

"An important goal of GENIE was to create a core logic chip set that allows systems manufacturers to design a single CPU board that can support multiple CPU architectures," said S.J. Lee, ALi Vice President of Technology. "They can design a generic high-performance system board which can support separate CPU cards with different CPU architectures, allowing high performance with available technology while minimizing redesign as new CPUs become available."

GENIE M1601 CPU and L2 Cache Controller

The M1601 is a high-performance MESI cache controller that supports single or multi-processors including the P54C/P55C, M1 and K5. Both APIC and SystemPro multiprocessor interrupt dispatch are supported.

The M1601 integrates the following functions: 1) the processor bus controller, 2) dual port high-speed TAG RAM, 3) L2 MESI cache controller, 4) high speed data buffer, 5) the host memory bus arbiter and 6) the host memory bus controller. The M1601 adopts a serial cache subsystem that can provide a concurrent dual bus, the processor local bus, and host memory bus, to do true concurrent data access. This true bus concurrency can achieve a balanced performance between the processor subsystem as well as the I/O subsystem. It can avoid an overall system throughput degradation even if there is an intensive I/O operation request. The M1601 is packaged in a 240-pin PQFP.

GENIE M1609 Memory and I/O Controller

The M1609 provides DRAM control and PCI bus bridge function to GENIE-based servers and workstations. The M1609 integrates the following functions: 1) DRAM controller, 2) ECC/Parity circuits, 3) I/O cache controller, 4) 256 byte write back I/O cache, 5) PCI bus interface circuits, and 6) Memory bus interface circuits. In order to achieve a balance of the system throughput, the design of the M1609 adopts a serial I/O write back cache technique to isolate the I/O bus from the memory bus. Thus the memory bus will be efficiently shared between the CPU subsystems and I/O subsystems.

ECC is built into the chip so no external ECC device is required. Among other features are EDO memory support, parity check enable/disable option, automatic memory sizing and a dual 64/128-bit memory data path. The circuit supports a fast burst mode transfer rate of 256 megabytes/sec. and has fast page or non-page mode support. It also features high-performance hidden and low power stagger refresh. The M1609 is supplied in a 208-pin PQFP package.