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ASIC Semiconductor Supports Mentor Graphics Design for Test Tools
Business Wire, Nov 25, 1996
SANTA CLARA, Calif.--(BUSINESS WIRE)--Nov. 25, 1996--ASIC Semiconductor Inc., the first full-service ASIC vendor that will also license its libraries, is now supporting design for test (DFT) methodologies and tools from Mentor Graphics (Beaverton, Ore.).
ASIC Semiconductor will incorporate the technology in all of the company's standard cell and gate array libraries, as well as recommended use and purchase of DFT software support tools.
"The increasing complexity and size of designs makes DFT technology ever more important," said Hsiado-Ping Lin, vice president of technology for ASIC Semiconductor. "Supporting Mentor Graphics allows us to implement DFT methodology more efficiently and saves time and resources for our customers."
ASIC Semiconductor and Mentor Graphics will jointly develop DFT libraries for all of the company's technologies, including the recently announced FS8000, 0.35 micron standard cell library and the company's 0.5 micron standard cell and 0.6 micron gate array libraries. All future technologies will support the various types of scan cells to comply with the scan methodology applied by Mentor Graphics.
To meet the comprehensive requirements of system-on-a-chip, ASIC and Mentor will also jointly develop testing methodologies in the areas of Built-in-Self-Test (BIST) for combinatorial logic, sequential logic and Random Access Memory (RAM).
ASIC Semiconductor International Corp., a privately held, California corporation founded in 1995, is dedicated to the design and manufacture of ASICs. The company was started by United Microelectronics Corp. (UMC), Faraday Technology Corp., K.C. Shih, H.P. Lin and other private investors. In January of 1996, ASIC Semiconductor acquired Pacific Semiconductor of San Jose, Calif.
CONTACT: ASIC Semiconductor International Corp.
Joseph Hong, 408/235-8888
or
Gelphman Associates
Rob Gelphman, 408/451-8420
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