Sun chooses Summit Design analysis tools; StateAlert and StateScore to be used in processor and ASIC designs for verification and regression testing

Business Wire, July 2, 1997

BEAVERTON, Ore.--(BUSINESS WIRE)--July 2, 1997--Summit Design, Inc. today announced it has licensed Sun Microsystems, Inc. to use Summit's Visual StateScore and Visual StateAlert design analysis tools under the terms of a recent three-year license agreement.

The agreement, signed earlier this year, followed a six-month-long detailed evaluation effort and allows Sun to use the tools on several next-generation processor and ASIC projects in any Sun development lab worldwide.

"We have inserted StateScore into our mainstream regression testing flow and StateAlert into the verification flow, in front of simulation," said Jim Gately, design verification manager of Sun. "We expect the tools to save us a substantial number of simulation cycles by providing crucial debugging knowledge and reporting potential design flaws that are difficult to find with simulation alone."

"This is a significant endorsement of the approach to FSM design analysis Summit gained through the Triquest acquisition," said Dr. Jay Roy, Summit's vice president of engineering for analysis products. "StateScore and State Alert are valuable additions to emulation and simulation technologies in developing high quality HDL for FSMs, saving schedule time and eliminating risk in cutting-edge designs."

Static Analysis and Code Coverage

StateAlert is a static analysis tool delivering exhaustive verification of finite state machines (FSMs) in a chip design. StateAlert uses Summit's Universal State Extraction (USX) technology to work directly from the user's complete Verilog HDL description. The tool uses formal methods, without the need of simulation or testbenches, to report potential design flaws in the FSMs. More than thirty checks are made including deadlock conditions, livelock conditions, equivalent states and inferred latches.

StateScore is an FSM code coverage tool using USX and the Verilog description to provide detailed reports on the effectiveness of testbenches in testing all possible FSM operations. Due to StateScore's FSM interpretation, the tool enhances traditional line level coverage by providing detailed reports, including state visitation, transition occurrence, unexecuted input conditions and sequence detection.

Summit Design, Inc. is a leading, international supplier of engineering software products for the creation of electronic systems and ICs using top-down design methodologies. Summit develops, manufactures and markets tools for design specification entry and design verification. The world's top electronics companies use Summit products to increase engineering productivity, reduce development time and improve the quality of their products.

Summit is located at 9305 S.W. Gemini Drive, Beaverton, Ore., 97008, 800/661-4333; http://www.summit-design.com . -0-

Note To Editors: Visual StateScore and Visual StateAlert are trademarks of Summit.

CONTACT: Summit Design, Inc.

John DiFerdinando, 503/526-6363

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Scott Seiden or Lou Covey, 415/637-8212