New Motorola DSP With Large On-Chip Memory and Coprocessor Greatly Boosts System Throughput; Small Package Permits Dense Packaging for Multi-Channel Applications

Business Wire, Sept 14, 1998

AUSTIN, Texas--(BUSINESS WIRE)--Sept. 14, 1998--A new digital signal processor chip introduced by Motorola (NYSE:MOT), that includes a large static RAM and a coprocessor on-board, makes possible a new level of system throughput performance - giving designers a major leap forward in design integration.

The chip design not only reduces wait states by allowing applications to run in the on-chip memory, it also uses the coprocessor to run applications in parallel, allowing the 56307 to effectively achieve 170 MIPS overall performance.

This novel chip has been packaged in a small 15 x 15 mm PGBA package and was designed to permit dense side-by-side board layout packaging for multiple-channel applications. This small package, coupled with high overall performance enables reduced chip count, low power consumption, and reduced overall system cost (i.e. high performance density).

"The 56307 is an aggressive offering by Motorola," said DSP market analyst Will Strauss of Forward Concepts. "With its very large on-chip SRAM, it's able to provide complete functionality without external RAM for many applications. The on-chip coprocessor will enable the 56307 to handle a greater number of communication channels."

The DSP56307 solution supports communications infrastructure applications with an independent Enhanced Filter Coprocessor (EFCOP), integrates 64K by 24 bits (192K bytes) of on-chip static RAM, six channels of DMA, a triple timer, serial communications, and other Input/Output (I/O), all in a 15mm square PBGA package.

"We feel the 56307 will generate considerable interest in the design community," said Daniel Artusi, vice president and general manager of Motorola's Wireless Infrastructure Systems Division. "The 56307 chip is available today and will permit engineers to extract maximum performance from minimum space."

Performance Density

This newest member of the 24-bit DSP56300 family of programmable DSPs, has an on-chip Enhanced Filter Coprocessor and processes filter algorithms in parallel with core operation, increasing overall DSP performance and efficiency. The chip utilizes a high performance, single-clock-cycle-per-instruction processing engine, a 56-bit barrel shifter, Instruction Cache, and Direct Memory Access (DMA) controller.

With the support of the on-chip coprocessor, the chip can attain 170 MIPS performance using an internal 100 MHz clock with 2.5 volt core and independent 3.3 volt I/O power. It is optimized for applications designed for multi-channel processing in communications and networking.

DSP56307 Architectural Features

The enhanced filter coprocessor provides a substantial performance edge in tasks such as voice coding and echo cancellation. The chip has a large, 192 Kbytes of on-chip static RAM which eliminates the need for external memory in many systems. The chip's six-channel DMA controller enables a great deal of parallelism, raising performance further.

The DSP56307 employs split power planes, separating the I/O and peripheral sections, which operate at 3.3 volts, from the processor core, which runs at 2.5 volts. This approach allows the rest of the system to maintain a congruous 3.3 volt environment while minimizing voltage and power dissipation in the new chip's core.

The new chip maintains core code compatibility with all other DSP56300-based devices, including application software, simulation models, application notes, and system development tools.

Target Applications

The 56307 serves as the basis for a wide variety of "DSP resource boards", in which an array of DSPs are used to process multiple channels of data in wireless, wireline, and network infrastructure equipment. For example, 56307-based boards can provide channel modem processing in the transceivers of cellular base stations.

It can perform transcoder functions, handling both voice coding and echo cancellation, in cellular mobile switching centers, and base station controllers. The chip can also perform voice coding and echo cancellation in wireline switching equipment.

To help engineers ease into the new architecture Motorola will be offering a free CDROM tutorial available by request from its web site.

Availability

The DSP56307 has already been deployed at customer sites in the U.S. and Europe. Parts are available immediately packaged in a 196-pin PBGA. In 10K quantities for 1999, the price for the DSP56307 is $47.00. Additional information can be accessed through the Motorola Web site at http://www.motorola-dsp.com

Development Tools

Motorola provides the Suite56 hardware and software development tools supporting the DSP56307. The Motorola Suite56 tools are complemented by a range of third-party tools including a compiler and debugger from Tasking and a debugger from Domain Technologies. These software tools are available on CDROM or can be downloaded from the Web at http://www.motorola.com/SPS/WIRELESS/dsptools/index.htm

A hardware evaluation module (EVM) kit is also available, enabling low-cost evaluation of the DSP56307 in a Windows environment. Regularly priced at $500, the EVM kit is promotionally priced at $250 for the remainder of 1998. To order an EVM kit, contact your local Motorola Sales office or authorized distributor and ask for part number DSP56307DKIT.