Cadabra Launches Alliance Partnership Program to Promote Interoperability Between EDA Tools for Library Development

Business Wire, June 28, 1999

SANTA CLARA, Calif.--(BUSINESS WIRE)--June 28, 1999--

Charter Cadabra Alliance Partners Validate Library Development

Methodology in Synopsys' Secured Users Resource Facility

Cadabra Design Automation Inc., the leading provider of automated transistor layout (ATL) tools, today announced the launch of Alliance, its highly-focused EDA partnership program.

Charter members include five EDA companies: Library Technologies, Inc., OEA International, Silicon Metrics Corporation, Silvaco International, and Synopsys, Inc. (Nasdaq:SNPS).

"Customer success is our primary reason for creating the Alliance partnership program," said Faysal Sohail, president and CEO of Cadabra Design Automation Inc. "Our objective is to create a highly productive, dynamic, and complete environment for library development flows so that circuit designers can unleash the power of Cadabra's ATL technology to improve density and speed, and optimize power. The Cadabra Alliance program provides a validated methodology that allows designers to push the design space exploration envelope for maximum results -- increasing product competitiveness and reducing time to market."

The goal of the Cadabra Alliance partnership program is to promote interoperability between EDA tools used in library design and development. To become a Cadabra Alliance member, a company must have a mutual customer base or offer a new technology that complements the library development flow.

Cadabra Alliance EDA partners provide extraction, characterization, and circuit simulation tools that complement Cadabra's CLASSIC-SC(TM) ATL methodology. The Alliance flow creates complete cell libraries needed to design with standard EDA tools.

Starting from a schematic transistor netlist, standard cell layouts are created with CLASSIC-SC and are used to qualify and evaluate a candidate EDA tool. The library design flow is exercised with the candidate tool using a relevant subset of cells. Interfaces between the tools are tested and the resulting library is validated. To facilitate library development, Cadabra and its EDA partners plan to enhance tool interfaces for optimal and seamless flow integration.

Charter Cadabra Alliance Partners Validate Library Development

Methodology in SPINE99 Secure Users Resource Facility

Cadabra developed a design library test vehicle using its Alliance partner tools to exercise the development flow. The design library was validated within the Secure User Research Facility (SURF) located at Synopsys.

The Spine99 initiative is a focused effort to improve interoperability among EDA companies. The Spine99 initiative establishes a design flow based on a commonly used "backbone" comprising Cadence and Synopsys tools, the "Spine". The "Spine" has clearly defined interoperability points for other EDA tools to plug into.

Cadabra used its automated transistor layout tools to produce a 0.18um TSMC technology layout. Extraction tools from OEA International (Cell-An) and Synopsys (Arcadia), and characterization tools from Library Technologies, Inc. (LibChar) and Silicon Metrics Corporation (CellRater), as well as circuit simulation from Silvaco International (SmartSpice) were integrated and validated using Synopsys' tools (Design Compiler and Power Compiler) in the SURF lab at Synopsys.

Richard Goldman, senior director, Strategic Market Development for Synopsys, said "We commend Cadabra for introducing an Alliance partnership program to promote interoperability of EDA tools. Synopsys, like Cadabra, is a firm believer that EDA vendors should take responsibility for interoperability of their tools. These solutions are being delivered to our mutual customers today through the Spine99 initiative, Synopsys's in-Sync, and TAP-in programs, and through Cadabra's Alliance partnership program."

About Cadabra Alliance Charter Members

Library Technologies, Inc. (LTI), headquartered in Saratoga, Calif., offers a set of integrated tools that verify the implementation of ASIC cells at the circuit level, synthesize the timing behavior of the cells, and automatically measure all of the timing and power parameters using popular circuit simulators, optimize cell parameters to meet performance and minimum power constraints. LTI tools enable users to produce accurate, reliable, verified and optimized libraries, eliminating design turnaround time due to traditional library problems. The simple and easy-to-learn ASIC Cell Description Language reduces post-layout user time for library generation down to a few simple statements.

OEA International, Inc. designs and licenses state-of-the-art signal integrity software for the electronic computer-aided design (ECAD) industry. OEA's software is designed to be extremely high performance and handle very complex models with a high degree of accuracy. OEA products are used to substantially increase engineering productivity and first time success in the design of interconnect and packaging technologies for sophisticated electronic systems and integrated circuits.

Silicon Metrics Corporation provides SmartIP_modeling solutions for deep-submicron (DSM) libraries that accurately predict the electrical behavior of integrated circuits. The company's innovative timing and power modeling technology provides breakthrough levels of performance, accuracy, quality and extensibility. Easily integrated into the synthesis, analysis and verification design flow, Silicon Metrics Silicon-smart models reduce the risk, cost and cycle time in the design of next-generation systems-on-a-chip (SOC). Silicon Metrics Corporation is a privately held company based in Austin, Texas with offices in Austin and San Jose, California. For more information, call 888/828-3736, or visit online at http://www.siliconmetrics.com.