Mentor Graphics Corporation Announces New Board Timing Solution That Cuts Weeks From Timing Verification Cycle

Business Wire, March 15, 1999

WILSONVILLE, Ore.--(BUSINESS WIRE)--March 15, 1999--Mentor Graphics Corporation (Nasdaq:MENT) today announced Tau(tm) 2.0 software, which allows the entire board timing verification process to be completed in one week.

In the past, design engineers have had to spend several weeks just creating models for board timing verification.

"In one week, we went from not knowing anything about Tau to being trained on the tool and performing timing analysis on our design," said H.J. Mikuteit, senior design engineer at Alcatel-SEL.

The Tau 2.0 offering provides a dramatic productivity gain by comprehensively solving the modeling problem, offering leading-edge analysis capabilities and improving ease of use.

"In the past, timing analysis was too painful because of the time involved in building component models, so it was performed very selectively," said Roger Yang, verification engineer at Cisco Systems. "We tend to rely on four to five weeks of prototyping to identify timing problems on our boards. With the Tau software and the project-modeling services that accompany the tool, we now complete the timing analysis of our boards in significantly less time. The tool is easy to use and we have received excellent support from Mentor Graphics. We expect to use this tool widely."

Mentor Graphics' modeling solution for board timing verification is comprised of modeling services, model libraries, interfaces to model formats and model development tools. The company provides project modeling services through which customers can obtain models for the components on their design within two weeks for a fee of $3,000. This also includes, at no additional cost, access to a model library of commonly used components such as processors, memory and glue-logic. To automate the creation of ASIC and FPGA models, the Tau 2.0 product interfaces with static timing analysis tools such as Mentor Graphics' Velocity(tm), Synopsys' Prime Time(tm), ViewLogic's Motive(tm) and Altera's MaxPlusII(tm). Timing diagrams, widely used to document component interface behavior, can also be used as models in Tau through its interface to Chronology's Timing Designer(tm). Finally, Tau has a high-level spreadsheet-based graphical user interface for easy and intuitive model creation.

In addition to solving the modeling problem, Tau 2.0 software offers state-of-the-art analysis capabilities. The product uses symbolic timing analysis technology to provide worst-case results in one pass and without false violations.

"With static timing analysis tools, we had to sift through hundreds of false violations. With the Tau product, we have been able to quickly focus on the real timing problems on our design," said Dieter Markus, verification engineer at Siemens. "We have found Tau's ability to take delay correlation into account to be particularly useful for the accurate analysis of memory subsystems on our boards. Exhaustive analysis using the Tau software rarely takes more than one minute for our designs."

Symbolic analysis reasons over the functional information in component models to automatically eliminate the reporting of false timing violations. In addition, through its delay correlation capability, symbolic analysis accounts for the tracking of delay within components and correctly handles the "common ambiguity" problem. Tau 2.0 software also performs clock tree analysis and computes the skew and phase shift between clocks, taking component and interconnect delay into account.

"We find most of our timing violations after taking interconnect delay into account," said Yang. "On a recent project, two violations were caused by unanticipated component placement and routing issues. Tau identified these violations, which had gone undetected using other approaches."

Tau reads interconnect delay information in Standard Delay Format (SDF) and so can be used stand-alone to perform post-layout timing verification. The Tau 2.0 offering can also be used pre-layout to aid in component selection. Finally, the software can be employed in conjunction with the Interconnectix(tm) tools from Mentor Graphics to perform timing-driven physical design. When used in this manner, Tau exports interconnect delay constraints in SDF format. These constraints are used within the Interconnectix tools to provide real-time feedback on the impact of physical design decisions such as component placement, net topology and routing on circuit timing.

With the Tau 2.0 product, design engineers have a timing analysis tool that does not burden them with a modeling problem, that provides accurate information on the timing margins for their design and that can also be used to drive the physical design process. All of this removes weeks from the time required to produce a reliable design that works at intended speeds.

Pricing and Availability

Current Tau software customers will receive the upgrade to the Tau 2.0 product as part of their active support agreement. New customers will be able to obtain the Tau 2.0 software for $35,000. The product will be available for shipment in April 1999.