Synplicity Enhances ASIC Prototyping and Partitioning Solution With Availability of Certify 2.1; Tool Enables Rapid Hardware Prototypes From RTL Code

Business Wire, Oct 4, 1999

SUNNYVALE, Calif.--(BUSINESS WIRE)--Oct. 4, 1999--

Synplicity, Inc. today announced the availability of an enhanced version of its register transfer level (RTL) partitioning and prototyping tool, Certify(TM) 2.1. The enhancements include several features that improve productivity for ASIC/SoC (system-on-a-chip) verification, including new pin assignment capabilities, new user interface, and partitioning aids. In addition, the new release includes support for Altera's (Nasdaq: ALTR) APEX and Xilinx's (Nasdaq: XLNX) Virtex programmable logic devices.

"The increasing complexity of today's ASIC and SoC designs has created verification problems that are impossible to solve using traditional simulation methods," said John Gallagher, director of product marketing for Synplicity. "The Certify tool facilitates PLD-based prototyping of ASIC/SoC designs by simplifying the partitioning and synthesis of complex RTL designs across multiple PLDs. Certify's enhanced synthesis algorithms ensure the highest performance prototypes."

Creating functional prototypes of a complete ASIC with multiple FPGAs is an approach that has traditionally been used by designers, but it is not widespread because of time required to manually partition a complex ASIC. Until recently FPGA architectures did not support the high clock speeds and large capacities needed to prototype an ASIC at or near full speed. Thus, designers have been using prototyping or emulation systems, which are both expensive and cannot operate near the internal ASIC clock speeds, to prototype their designs.

Certify directly addresses both the cost and performance needs of designers by enabling the creation of high performance FPGA-based prototype boards, typically in less than one month for less than $20,000. These ASIC-specific "Certify-defined boards" offer the highest internal clock speeds for prototyping. Certify can also be used with reconfigurable prototyping systems, such as the Aptix System Explorer, to handle a wide range of ASIC designs.

Certify 2.1 Highlights

The new Certify 2.1 includes several features that enable increased productivity for ASIC/SoC designers, including new pin assignment capabilities, as well as a new user interface and enhanced partitioning aids. With Certify 2.1, designers gain a more than 25 percent improvement in cycle time for partitioning over Certify 1.1.

Certify's new user interface is optimized for handling SoC designs by providing detailed feedback on black-box timing models used for non-synthesizable components, trace delays on the prototype board and full cross-probing of all RTL level views of the design. Prototype performance and time-to-market are enhanced by using the new partitioning aids in Certify 2.1, including decomposition of large MUXs, bit-slicing of large primitives and the ability to "zipper" functional blocks based on inputs or outputs. As with all other debug and partitioning aids, such as automatic probe-point creation and logic replication, the new features do not modify the source RTL code, a key difference from competitive solutions.

In addition, the new release now includes support for Altera's APEX programmable logic devices and Quartus place and route software. Certify also supports Xilinx's Virtex devices and Altera's Flex 10K devices.

"Many ASIC designers are not fully aware of the rapid technology advances in programmable logic devices," said Erik Cleage, senior vice president of marketing at Altera. "Our APEX 20K family, supported by Certify, will allow ASIC designers to include up to 1.5-million gates in a single programmable logic device with embedded memory and third-party IP. Certify eases the process of combining several APEX devices to create prototypes of multi-million gate ASICs."

Certify is the industry's only prototyping and partitioning tool to operate at the RTL level of a design while incorporating synthesis estimates of area and connectivity for the targeted PLDs. This unique approach results in higher productivity than current gate-level partitioning approaches, which require multiple iterations to achieve the ideal partitioning of the devices.

Certify's Core Technology

Leveraging Synplicity's core synthesis and partitioning technologies, Certify allows designers to create functional hardware prototypes of their ASIC at the RTL level, prior to synthesis. Verification at this early stage of design enables faster time-to-market, especially for the one-million-gate-plus ASIC/SoC designs used for multimedia and communications applications.

Certify is based on Synplicity's proprietary Behavior Extraction Synthesis Technology (B.E.S.T.(TM)) and the Partition Aware System Synthesis (P.A.S.S.) algorithms. Unlike traditional methods which optimize at the gate level, Synplicity's B.E.S.T. algorithms maintain high levels of abstraction through much of the optimization process, resulting in unprecedented levels of performance. The P.A.S.S. technology, an extension of Synplicity's synthesis technology, utilizes partitioning information in the synthesis process, providing the highest productivity and quality of results for the ASIC/SoC prototype.