Tessera and Mitsui High-tec Partner On Development of Next Generation Chip-Scale Packaging Technology; WAVE Technology Will Expand Tessera's CSP Offerings

Business Wire, Feb 29, 2000

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 29, 2000

Tessera(R) Inc., the industry's leading provider and licensor of chip-scale packaging (CSP) technology, today announced a licensing agreement and partnership with Mitsui High-tec Inc. for Tessera's new WAVE(TM) (Wide Area Vertical Expansion) CSP technology. According to the terms of their agreement, Tessera and Mitsui High-tec, a major semiconductor assembler and lead frame manufacturer, will partner on the development of a high volume single-chip manufacturing process for Tessera's WAVE technology, followed by collaborative development of a wafer-level WAVE manufacturing process. Tessera's first WAVE prototype is a high-speed SRAM being developed with a major chip maker.

"Mitsui High-tec looks forward to growing our relationship with Tessera as we partner to develop single chip and wafer-level manufacturing processes for WAVE technology," said Satoshi Nagata, president and CEO of Mitsui High-tec Inc. "Co-developing these processes with Tessera guarantees us early time-to-market, uniquely positioning Mitsui High-tec as the first assembler capable of offering the industry's most advanced chip-scale package to semiconductor manufacturers."

Tessera is partnering with Mitsui High-tec and other industry leaders in order to provide its customers and licensees with a wide range of CSP solutions. To accelerate development and broad adoption of its WAVE technology, Tessera and Mitsui High-tec will combine resources on process development. This will significantly reduce the amount of time needed to develop a cost-effective high volume WAVE manufacturing process, and will enable Tessera to bring the WAVE technology and manufacturing process to market in parallel.

"Our partnership with Mitsui High-tec is a critical step in Tessera's plan to accelerate industry adoption of new CSP technology," said Bruce McWilliams, president and CEO of Tessera. "Tessera's partnerships with other industry leaders will drive standards in CSP and enable Tessera to meet growing demands for new technology in the shortest time possible."

Driven by the industry's need for wireless communications and Internet access devices to be smaller, faster and cheaper, Tessera's CSP technology enables the semiconductor industry to manufacture packaged integrated circuits optimized for size, performance and reliability. Tessera's WAVE technology, an evolution of its industry leading (mu)BGA(R) package, is one of a number of CSP solutions that Tessera is licensing to the semiconductor industry.

The Next WAVE in IC Packaging

WAVE technology was developed as an enhancement to Tessera's (mu)BGA CSP technology, enabling greater flexibility, lower cost and broader applicability. WAVE will extend the market for Tessera's CSP technology into high pin count, high-performance applications such as high-speed memory, ASICs and microprocessors. WAVE technology enables CSPs with standard footprints by eliminating most ball placement and I/O routing restrictions. WAVE will also accommodate a number of different types of bond pad layouts, including area array, peripheral lead and center lead bond pads.

WAVE technology has the same high performance and small form-factor advantages of Tessera's (mu)BGA CSP technology, but enhances them with the standard footprint and adaptability benefits offered by traditional BGA packages. The ability to accommodate standard footprints will allow OEM manufacturers to select from multiple component sources, driving down the cost of assembling ICs using CSP technology. WAVE technology is also extremely well suited to die shrinks and fan-out applications, enabling OEMs and third party board manufacturers to maintain board layouts and use a single package across product families and throughout product life cycles.

Wide Area Vertical Expansion Technology

WAVE technology bonds all of an IC's electrical interconnects in parallel -- as opposed to the single-point or wire bonding methods used today in most BGA and CSP packages -- greatly reducing assembly time and cost over other CSP solutions. This massively parallel bonding is followed by the elastomer injection process. This process involves injecting the compliant encapsulant into the assembly frame, which causes the narrow gap between the polyimide tape and the silicon to vertically expand, three-dimensionally, forming all the leads in one step. The spring-like shape of these leads allows them to flex extremely well in three dimensions with extremely low stress, resulting in a highly reliable CSP.

Since WAVE technology is compatible with the existing (mu)BGA assembly and materials infrastructure, licensed assemblers will only need to alter a minimal number of steps on their existing (mu)BGA lines to accommodate the WAVE process. Once the WAVE process is fully developed, assemblers will be capable of running both WAVE and (mu)BGA packages on a single line in the same foundry.

WAVE technology is based on the same underlying concept as Tessera's (mu)BGA package -- "Compliant CSP" technology. Tessera's technology places its patented compliant layer between the silicon die and the package substrate to absorb stress caused by differing rates of thermal expansion between the die and the circuit board. As package dimensions shrink, this stress causes the solder balls on a traditional package to detach or break. Tessera's technology accommodates this stress in the compliant layer -- essentially enabling the smallest possible semiconductor package dimensions with the high reliability required in all CSP solutions.