Green Hills Software To Provide Integrated Development Environment For MIPS Technologies' MIPS32 and MIPS64 Processor Cores

Business Wire, March 13, 2000

Business Editors

SANTA BARBARA, Calif.--(BUSINESS WIRE)--March 13, 2000

Green Hills Named "MIPS Technologies Preferred

Tools Provider" For Both Cores

Green Hills Software today announced a new technology development and cooperative marketing agreement with MIPS Technologies Inc.

Per the agreement, Green Hills will port its MULTI 2000 Integrated Development Environment and Optimizing Compilers to MIPS' new MIPS32(TM) 4Kc(TM) (code named Jade) and MIPS64(TM) 5Kc(TM) (code named Opal) 32- and 64-bit processor cores. MIPS, in turn, will introduce Green Hills as "MIPS Technologies preferred tools provider," giving Green Hills a leg up with new MIPS Technologies core prospects.

"The MIPS(R) processor architecture has always been a key component of our embedded strategy," said John Carbone, vice president of marketing at Green Hills. "Our compilers and development environment have been optimized to take full advantage of the MIPS processor architecture's superior mix of high performance, low power consumption, and reduced memory usage. We're extremely pleased to have been selected as MIPS Technologies' preferred tools supplier for the MIPS32 4K and MIPS64 5K architectures. This raises the bar for high-performance, low-power embedded computing."

"Easy-to-use integrated development environments are the key to maximizing productivity for the large programming teams that work on today's complex embedded software projects," said Brian Knowles, vice president of marketing for MIPS Technologies Inc. "Efficient compilers are the key to reaping the performance and power/memory savings features of the MIPS-based processor architectures. We're happy to have Green Hills on board for the MIPS32 and MIPS64 architectures."

The MIPS32 4Kc (Jade) is a high-performance, synthesizeable, 32-bit RISC processor core optimized for low-power, battery-operated, system-on-a-chip ASIC applications. Fully compatible with the MIPS32 architecture, Jade supports R3000(R) and R4000(R) user-level code and is optimized for running embedded operating systems. The Jade core and its bus interface operate at speeds from 0-200 MHz, consuming just 2 mW/MHz when equipped with 16 kbytes of cache and fabricated in a typical 0.25-micron process. The core features a five-stage pipeline with branch control and single-cycle execution for most instructions, a 32-bit entry MMU, and up to 16 kbytes each of 4-way, set-associative instruction and data cache.

The MIPS64 5Kc (Opal) is a high-performance, synthesizeable 64-bit RISC processor core optimized for low-power, battery-operated, system-on-a-chip ASIC applications. Optimized for embedded operating systems, Opal runs user R4000(R) and R5000(R) code, features a peak clock frequency of 375 MHz, and consumes just 1 mW/MHz when fabricated using a typical 0.15-micron CMOS process. Opal features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface for FPUs, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.

The MULTI 2000 IDE, together with Green Hills' family of optimizing C, C ,EC , and Ada95 compilers, automates all aspects of embedded software development for MIPS processors, including the MIPS32 4Kc (Jade) and MIPS64 5Kc (Opal) architectures. Available for Windows 95/98, Windows NT, and Unix host platforms, the MULTI IDE features a window-oriented editor, source-level debugger, graphical program builder, run-time error checker, version control system, performance profiler, optimizing profiler (CodeBalance(TM)), and real-time RTOS EventAnalyzer. MULTI also features an instruction set simulator (SimMIPS) that allows programmers to develop and test code on a PC or workstation without the need for the target hardware.

The heart of the MULTI environment is a source-level debugger that supports process- and system-level debug. The debugger provides a separate window for each process, supports mixed assembly and high-level language formats, includes a language-sensitive expression evaluator, and provides special support for C (such as a Class Browser, object display and template debug capability). The MULTI 2000 debugger is fully RTOS aware, which enables designers to debug and tune their applications at a task level. With the MULTI debugger, designers working with popular RTOSs like ThreadX(TM) can start and stop threads, and monitor OS resources like buffers, queues, and semaphors.

MULTI 2000's EventAnalyzer, fully integrated with the ThreadX RTOS, builds on the debugger's real-time capabilities, graphically displaying system and application events on an expandable timeline in real time. Operating like a high-level logic analyzer, the EventAnalyzer GUI displays all context switches, ThreadX API calls, and interrupts in a time-relative manner using intuitive icons. The EventAnalyzer also provides versatile navigation capabilities that allow programmers to zoom in and out of the timeline to obtain greater detail about particular event sequences.