Xilinx and Qualis Partner to Develop Internet-enabled Design Reuse Methodology for ASIC and FPGA Designers

Business Wire, March 20, 2000

Business Editors & High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--March 20, 2000

In a move to expand the Design Reuse initiative that launched last November, Xilinx (Nasdaq:XLNX) joins Qualis in providing the industry's first Internet-enabled reuse methodology guide for both FPGA and ASIC design.

The FPGA Reuse Field Guide text contains leading design techniques for creating and leveraging reusable VHDL- and Verilog-based designs. Further, a comprehensive, interactive training series using the Xilinx(R) FPGAs, which covers HDL coding styles as well as recommendations for developing design specifications, design archive structures and design verification guidelines, is jointly available from Xilinx and Qualis.

"Central to the partnership, Qualis and Xilinx will work together to define a best practices methodology for leading edge FPGA designs," said Michael Horne, president of Qualis Design Corp.

"The fruits of the partnership will be a flexible methodology that serves the best interests of SOC (System-on-a-Chip) and SORC (System-on-a-Reprogrammable Chip) designers because it now gives them the freedom to choose the best implementation device -- FPGA or ASIC -- independent of design application."

Merging ASIC and FPGA reuse methodologies

ASIC and FPGA design methodologies are merging as the size and speed of FPGAs approach that of mainstream ASICs. FPGAs are on the leading edge of technology advances with many design starts or prototypes in FPGAs migrating to ASICs or remaining in FPGAs for production.

Having a common reuse methodology allows for easy migration from one technology to another and maximizes the ability to migrate designs within technologies. With this methodology, intellectual property (IP) technology can be used and reused among designers to shed critical time in the production cycle. This guide will provide ASIC and FPGA designers the information needed to target FPGAs in a common methodology environment.

The FPGA Reuse Field Guide is more than a coding style guide: it provides an overview of the economic issues involved with design reuse; detailed information about project specifications; project management and organization; and project verification and qualification.

"Partnering with Qualis allows our customers to use the same design reuse strategy for ASIC and FPGA designs. By using the recommendations from Qualis, designers have the flexibility to choose the best IC technology for a project," said Mark Aaldering, senior director of Xilinx IP Solutions Division.

Industry Leading Methodology

The FPGA Reuse Field Guide is based on Qualis' Productive Knowledge(TM) information technology. As the industry's leading independent authority on design reuse methodologies for ASIC designers, Qualis has deep, proven experience in design for reuse and ultra large ASIC design.

The Field Guide base technology is the culmination of years of developing optimal, tool-independent methodology flows. Now FPGA designers have a reuse Field Guide that focuses on the same issues ASIC designers face, such as determining the cost of reuse; building a corporate reuse infrastructure and review team; specification writing; designing a bus hierarchy; verification planing and process; HDL coding and synthesis guidelines; source management; and bug and issues tracking.

The Reuse Value

Today's sub-micron technology makes multi-million gate FPGAs possible and this leads to a shift to using FPGAs for SOC designs, making them SORC designs. Still, the ability to leverage IP from third parties or internal design teams through design reuse methodology is the most effective to increase a designer's productivity.

"The productivity gap exists for everyone. Design reuse is a source of competitive advantage allowing companies to reduce their time-to-market. This is a critical decision factor for today's designers who know that the first supplier to market typically grabs 70 percent of the market share," said Qualis' Horne.

"We know that many of our customers have been grappling with how to start the adoption of design reuse within their company. This Field Guide will give them the knowledge and technology to get started quickly," added Aaldering.

Product availability

The first release of the Field Guide is available in Adobe Acrobat and hard copy formats free of charge to Xilinx customers. Enhancements to this Field Guide include a design reuse strategy for the Xilinx FPGA families. An extensible, comprehensive Reuse Methodology Field Guide and supporting training and consulting is also available from Qualis. Go to www.xilinx.com/ipcenter or www.qualis.com/methodology.html for more information.

This partnership with Qualis marks the continuing effort from Xilinx in the area of design reuse promotion. It complements the Xilinx publication of the Xilinx Design Reuse Methodology for ASIC and FPGA Designers manual, a supplement to the "Reuse Methodology Manual" (RMM) from Synopsys and Mentor Graphics, announced last year.

The Xilinx reuse manual provides guidelines for designers who want a common strategy for reusing intellectual property regardless of whether it was developed for ASICs or for FPGAs.