NEC Electronics Selects Synplicity's Verification Tool for New ASIC/SOC Design Methodology; NEC is First ASIC Vendor to Endorse RTL Prototyping

Business Wire, May 15, 2000

Business Editors/High Tech Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--May 15, 2000

Synplicity, Inc. today announced its register transfer level (RTL) partitioning and prototyping tool, Certify(TM) has been incorporated into NEC Electronics' new system-level design methodology, code-named ACE-2. With this announcement, NEC becomes the first ASIC vendor to incorporate RTL prototyping into its design flow. Using Certify within NEC's ACE-2 open system design methodology, designers can build FPGA-based prototype boards to quickly and easily verify complex SoC designs.

"One goal of our ACE-2 initiative is to provide customers with a methodology for demonstrating and evaluating their designs at the earliest stage," said Kazu Yamada, general manager of NEC Electronics' Technology Foundation Division. "Using Synplicity's Certify tool at the RT level, designers can build FPGA prototype boards running at- or near- system speed -- between 10 and 60 MHz -- providing the performance needed to evaluate real-world performance."

"Over the past year, our customers have turned to Certify to help them overcome the ASIC verification bottleneck and meet their ever-shrinking time-to-market windows," said Andy Haines, vice president marketing for Synplicity(R). "By providing a complete system-level-design methodology, including Certify for prototyping, NEC's ACE-2 initiative promises to continue to reduce design turnaround time for complex SoC designs."

About Certify

Leveraging Synplicity's core synthesis and partitioning technologies, Certify operates at the RT level, allowing designers to create functional hardware prototypes of their design prior to ASIC synthesis. This unique approach results in higher performance and productivity than gate-level partitioning approaches, which require multiple iterations to achieve a suitable partitioning of the devices, and enables faster time-to-market, especially for the one-million-gate-plus ASIC/SoC designs used for multimedia and communications applications.

Certify also enables extensive verification that previously could not be performed at the RT level without weeks of manual effort and modification of the RTL code. The creation of a functional hardware prototype at the RT level enables ASIC designers to perform the following tasks at or near system speed: hardware/software co-verification; algorithm development and verification; verification of intellectual property, either cores or library elements; system software development and debugging, verification of system-level protocol compatibility and early system/product development with FPGAs.

About Synplicity

Founded in 1994, Synplicity Inc. delivers the benefits of logic synthesis and embedded synthesis technologies to programmable logic and ASIC designers by developing fast, easy-to-use, affordable tools with extremely high quality of results. Synplicity products support industry-standard design languages (VHDL and Verilog), run on popular platforms (Windows 95/98, Windows NT and UNIX) and support leading PLD manufacturers. Synplicity is a Platinum member of the Cadence Connections Program (NYSE: CDN), Synopsys Liberty Program (Nasdaq: SNPS), and other industry standards organizations. The company is located at 935 Stewart Drive, Sunnyvale, Calif. 94086. Telephone: 408/215-6000; Fax: 408/990-0290; E-Mail: info@synplicity.com.

The specific features, functionality and release timing of any new products or new versions of current products remains at the sole discretion of Synplicity, Inc., and no warranty is made as to when or if specific features, functionality or releases may occur.

Note to Editors: Synplicity is a registered trademark and Certify is a trademark of Synplicity, Inc. All other brands or products are the trademarks or registered trademarks of their owners.