STMicroelectronics Tapes Out High-Performance, Mixed-Signal Communications Chip Using Synopsys' Physical Synthesis Design Flow

Business Wire, May 17, 2000

Business Editors/High-tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 17, 2000

Physical Compiler Provides Quick Timing

Closure for Challenging Design

Synopsys, Inc. (Nasdaq:SNPS), today announced STMicroelectronics' successful tape out of a high-end 150 MHz, 0.18 micron mixed-signal device for use in satellite communications applications.

Using Synopsys' Physical Synthesis tool, Physical Compiler, STMicroelectronics was able to achieve single-pass timing closure and completion of the design in a matter of only two days-eliminating approximately 90 percent of their previous design time.

"This design success results from our partnership with Synopsys to provide our customers with predictable, one-pass timing closure for some of the most challenging submicron designs," said Phillipe Magarshack, Group VP at STMicroelectronics' Central R&D. "Because of its previous, proven performance, it comes as no surprise to us that Synopsys' Physical Compiler performed as well as it did on such a complex design. It provides the type of design predictability you learn to expect from a solid physical synthesis tool."

"STMicroelectronics is a strong user of Synopsys' Physical Synthesis tools, including Design Compiler, PrimeTime, and Arcadia. Because the tools are fully integrated, plugging Physical Compiler into our design flow was very easy," said Jean Pierre Geronimi, Director of CAD at STMicroelectronics' Central R&D. "In less than one week, we had the tool up and running, and immediately began to experience increased productivity. In the end, we were able to reduce our design time from approximately four weeks to two days, achieving one-pass timing closure on what we consider to be a very difficult design containing 11 RAMs and a high-performance 150 MHz clock."

"The true measure of a successful timing closure tool, is in the tape out success of an extremely challenging design, such as the satellite receiver chip from STMicroelectronics," said Sanjiv Kaul, vice president and general manager for Synopsys' Physical Synthesis business unit. "More and more, our customers are putting Synopsys' Physical Synthesis flow to the test on rigorous applications such as graphics, wireless, advanced processors and communications, and pleasantly discovering they can count on the predictable results."

Synopsys' Physical Synthesis Solution

Physical Synthesis is the flow pioneered by Synopsys to address the implementation challenges of next-generation ASIC and system-on-a-chip (SoC) designs. Physical Synthesis brings key physical designs considerations to the front-end, allowing RTL designers to achieve the highest quality (area, timing and power) quickly. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement tool and FlexRoute top-level router. It leverages industry-standard tools like Design Compiler(TM), Module Compiler(TM) and PrimeTime(R). Its proven interfaces to third-party solutions allow it to easily plug into an existing design flow.

Synopsys will showcase products designed with Physical Synthesis at the Design Automation Conference in Los Angeles (Booth No. 4201), June 5-8, 2000.

Pricing and Availability

Physical Compiler is available starting May 22. Pricing for a single-user, one-year term license begins at $100,000. Support and maintenance options vary and are in addition to the product license.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Physical Compiler, Design Compiler, Module Compiler, PrimeTime, Arcadia and FlexRoute are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.