Synplicity Automates ASIC Verification Software; New Quick Partitioning Technology Eliminates Bottleneck in Prototyping Flow

Business Wire, August 20, 2001

Business Editors/High-Tech Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--Aug. 20, 2001

Continuing to tackle designer productivity issues, Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has automated its Certify(TM) verification synthesis software to speed the development of FPGA-based ASIC prototypes. The software can now perform many time consuming tasks automatically, including partitioning, gated-clock conversion and pin multiplexing, shaving days or weeks off of the prototyping process. Featuring Synplicity's new Quick Partitioning Technology, the Certify software now provides designers with the capability to automatically partition an ASIC design onto multi-FPGA custom boards for the development of ASIC prototypes. Additionally, Synplicity has enhanced the Certify software's automatic gated-clock conversion and Certify pin multiplexing (CPM) features to increase the speed and performance of ASIC prototypes.

"Synplicity has consistently developed software solutions that help enable designers to innovate and broaden their design goals," said Andy Haines, vice president of marketing for Synplicity. "By increasingly automating our software and making it easier to use, we have made it possible for most designers to become proficient users of our solutions and obtain high quality of results in the least amount of time. With the development of new automated features, including our Quick Partitioning Technology, we are continuing our goal of providing designers with leading-edge design solutions and speed time-consuming design tasks."

First introduced in May 1999, the Certify software is the industry's first registered transfer level (RTL) prototyping solution that enables designers to create functional hardware prototypes of their ASIC design at the RTL, prior to ASIC synthesis. Verification at this early stage of design results in a dramatic increase in productivity and enables faster time to market. Today, the Certify software is being used by dozens of users to solve their ASIC verification needs.

Jerry Worchel, president, inSearch Research, said, "Traditionally, prototyping an ASIC design onto an FPGA board has been a time-consuming process that could only be performed by very experienced design engineers, severely hindering design team resources. By further automating its Certify software to perform many of the tedious tasks involved in prototype development, Synplicity has enabled design engineers, regardless of their prototyping experience, to quickly and easily take advantage of the verification benefits FPGA-based prototypes offer."

Quick Partitioning Technology

With the addition of the Quick Partitioning Technology in the Certify 5.0 software, Synplicity has automated one of the most time-consuming processes in prototyping -- partitioning. Traditionally, a designer needed to use the Certify software's guided interactive partitioning feature to partition a design manually. Following the designer's manual effort, the software would provide users with feedback to assist with any decision-making regarding the design, such as I/O usage and area usage. With the Quick Partitioning Technology, a user can optionally set goals for area and I/O usage on the FPGAs in the prototype, then run the Certify software to automatically partition the design onto a custom board.

Early benchmark results show typical ASIC designs that are run through the Certify software using Quick Partitioning Technology are able to be automatically partitioned onto a custom board, often in under a minute. The same design manually partitioned onto a custom board by an experienced designer required several hours or more, on average. On very complex designs, the savings in partitioning time can be days. Additionally, when design changes are made during the verification process with the prototype, the functional changes can be made directly to the original RTL and automatically re-partitioned resulting in even more time savings.

The new Certify software provides greater flexibility for designers trying to meet specific design requirements by offering both automated and manual partitioning capabilities, or any combination of the two. This feature enables a designer to either manually place timing-critical blocks in specific FPGAs and then let the Certify software automatically partition the rest of the design, or let the Certify software automatically partition the whole design before manually partitioning parts of the design.

Additional Automation-Specific Enhancements to the Certify Software

Continuing to speed the prototyping process, Synplicity has enhanced a key ASIC conversion feature already in the Certify software, the ability to recognize additional gated-clock elements in an ASIC when they are converted into an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the software can now also detect clock trees with inferred and instantiated memories, inferred and instantiated latches, instantiated registers, shift registers, state machines, and counters. By developing these unique algorithms that enable the Certify software to recognize complex gated-clock elements, Synplicity has eliminated the traditionally time-consuming task of manually converting gated-clock elements.