Altera Unleashes Quartus II Development Software - The New Software Standard for System-on-a-Programmable-Chip Design

Business Wire, Jan 29, 2001

Business Editors/High Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 29, 2001

Altera Corporation (Nasdaq:ALTR), a leading programmable logic device (PLD) supplier, today announced the availability of the new Quartus(TM) II development software. Altera's Quartus II development software delivers 30-60 percent higher design performance (fMAX) and a 50 percent compile time reduction over the existing Quartus version 2000.09 by incorporating new algorithms with Altera's PowerFit(TM) fitter technology. From the introduction of Quartus development software in 1999 to this initial release (version 1.0) of the Quartus II development software, compile times have been reduced by a factor ranging from 6-15 resulting in the fastest compile times in the industry. Customers comparing Altera's high-density solution today versus that solution one year ago will see design performance (fMAX) improve by a factor of 2. In addition, Quartus II development software provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design with support for Excalibur(TM) embedded processor solutions and new system level design features including the industry's first integrated power analysis tool and enhancements to system level verification.

"Customers are searching for a development environment that delivers superior designer productivity," said David Greenfield, Altera director of development tools marketing. "The Quartus II development software hits this target by doubling design performance in a fraction of the time."

The Industry's Fastest Compile Times

Altera's Quartus II development software dramatically improves compilation times by taking advantage of new timing-driven router algorithms. The new router algorithms featured in the Quartus II development software intelligently prioritize PLD routing resources for critical timing paths based on the timing requirements defined by the designer. Critical timing paths are optimized first to achieve timing closure faster and reduce overall compile times.

The Quartus II development software also supports Altera's new APEX(TM) 20KC device family, which is manufactured using an advanced 0.15-micron process with all-layer copper interconnects. Altera's APEX 20KC device family provides a 20-30 percent performance (fMAX) improvement over the APEX 20KE device family.

SOPC Design Capability

In addition, the Quartus II development software supports Altera's new Excalibur embedded processor solutions. The Excalibur embedded processor solutions, which consist of ARM(R), MIPS(R), and Nios(TM)-based processor solutions, allow designers to develop an entire system on a single programmable chip. For SOPC design, developers require an integrated design environment that integrates both hardware and software design. The Quartus II development software extends the user scope beyond hardware by incorporating the new SoftMode(TM) workflow that offers C/C compilers and debuggers in a fully integrated development environment.

Another designer productivity enhancement in Altera's Quartus II development software is the industry's first integrated power analysis tool. The PowerGauge(TM) analysis tool uses the designer's simulation files to link the power consumption estimate with customer-specific design files and operating parameters. Integrated power analysis enables Altera customers to identify and therefore optimize system level power consumption earlier in the design cycle.

The Quartus II development software version 1.0 includes a new framework to enhance team-based SOPC design flows. Incremental design capabilities based on the new framework will roll out in Quartus II version 1.1 in Q2, 2001. Incremental design enables team members to design a block of custom logic or add a block of pre-verified intellectual property (IP) to a design, make pin and timing assignments to that block, verify functionality and performance, and then lock the placement and performance of the block. All timing optimization is done on the individual block level with this new incremental design flow. System designers can focus on the integration and performance of the entire system, knowing that the incremental design methodology guarantees the performance of the individual blocks. Incremental design enables teams to implement multimillion-gate PLD designs with optimal efficiency.

About Quartus II Development Software

Altera's Quartus II software delivers superior designer productivity and supports system-level designs with features including the PowerFit fitter technology, support for multi-million gate devices, and integration with third party tools. Also, with support for the Excalibur embedded processor family, it extends the user scope beyond hardware by including a software workflow that offers C/C compilers and debuggers in a fully integrated development environment. The Quartus II software supports major operating systems, including Windows 2000, Windows NT, Windows 98, Sun Solaris, and HP-UX.

Pricing and Availability