Cadence Announces Sign-off Support From LSI Logic for Cadence SP&R In ASIC Design Flows

Business Wire, July 16, 2001

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--July 16, 2001

LSI Logic Provides Sign-Off Support for Cadence

Physically Knowledgeable Synthesis and the Cadence

Common Timing Engine in the FlexStream ASIC Design Kit

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced LSI Logic (NYSE:LSI) sign-off support for Cadence SP&R. This includes Cadence Physically Knowledgeable Synthesis (PKS) and the Cadence(R) common timing engine (CTE) used in PKS and in Cadence BuildGates(R) synthesis. LSI Logic will integrate PKS, BuildGates, and the CTE into its FlexStream(TM) application specific integrated circuit (ASIC) design kit.

"The ASIC design hand-off process for LSI Logic customers will be significantly enhanced by incorporating PKS, BuildGates, and the Cadence CTE into the FlexStream ASIC methodology," said Thomas Daniel, vice president of ASIC Technology at LSI Logic. "Our customers can now be confident that the timing achieved on a design during synthesis will correlate with its post place and route final timing as a result of using the same embedded timing, placement, optimization, and global routing engines through synthesis and physical implementation."

Cadence and LSI Logic collaborated closely with Ericsson Microwave Systems AB to test the design flow. Ericsson Microwave, a user of Physically Knowledgeable Synthesis for front-end physical synthesis, applauds this endorsement by LSI Logic. The close working relationship between Cadence, LSI Logic, and Ericsson Microwave during the project was vital for the successful qualification of PKS into FlexStream 3.0.

"Our SP&R solutions provide designers with a superior methodology for addressing timing closure on next-generation, deep sub-micron, and SoC designs," said Kevin Moynihan, vice president, Cadence SP&R. "The integration of Cadence SP&R technology in the FlexStream ASIC design kit brings LSI Logic and our mutual customers an increase in productivity with front-to-back correlation for one-pass timing closure from RTL to GDSII. Using the sign-off quality engines embedded in the SP&R solution allows designers to statically verify circuit timing to efficiently achieve timing closure."

The Cadence CTE identifies critical timing paths, analyzes clock network skew, and checks set-up and hold-time requirements for a circuit, all without the need for a standalone sign-off static timing analyzer. Designers are able to identify and repair timing problems without leaving the design environment. By using its CTE throughout the SP&R flow, Cadence not only reduces constraint generation and verification time, but also enables excellent timing correlation between synthesis and place-and-route.

About Cadence SP&R

Cadence SP&R is the industry's first unified synthesis/place-and-route system. It consists of PKS physical synthesis and Silicon Ensemble(TM) PKS (SE-PKS) optimization place-and-route. SP&R features correlation within three percent through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

About Cadence PKS Physical Synthesis

Cadence PKS is the most complete and tightly integrated physical synthesis offering available today. It achieves tight correlation with final routed results because its synthesis, timing, and placement, and true global routing engines are integrated into the same tool. This integration also provides better quality-of-results, seen in the frequency and area of the design.

About BuildGates Synthesis

BuildGates logic synthesis enables customers to synthesize multi-million gate designs rapidly with superior results. BuildGates features the Cadence common timing engine, which provides high-capacity and high-performance timing analysis. It also includes a distributed synthesis capability that leverages networked compute environments to dramatically reduce synthesis runtime for large designs.

Pricing and Availability

BuildGates and PKS synthesis products are available worldwide for UNIX-based workstations from Hewlett-Packard and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list prices start at $12,000 and $100,000, respectively. Cadence Silicon Ensemble PKS optimization place-and-route's one-year U.S. list price starts at $400,000. For information on international pricing, please contact the local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.