Synplicity Announces Industry's First ASIC Synthesis Software Optimized for Designer Productivity

Business Wire, June 4, 2001

Business Editors/High Tech Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--June 4, 2001

Company Enters ASIC Synthesis Market with Fast, Easy-to-Use,

Powerful Solution

Synplicity Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today introduced the industry's first timing-driven ASIC synthesis product optimized to improve productivity for the majority of ASIC designers. Leveraging the proprietary synthesis algorithms that have made Synplicity's FPGA synthesis and ASIC verification products successful, Synplicity's new Synplify ASIC(TM) software is able to provide designers with a fast, easy-to-use and powerful ASIC synthesis solution. For designers who need the fastest time to market, the software boasts runtimes up to 15 times faster than traditional synthesis products. Further improving productivity, the Synplify ASIC software offers a unique "top-down" design methodology that enables designers to perform timing-driven synthesis on up to two-million-gate designs in a single operation, supporting matching hierarchy and constraints in synthesis and place and route steps.

"In the FPGA synthesis market, we believe we have provided more than 1,400 design organizations with a fast and easy-to-use solution that obtains high quality of results," said Ken McElvain, co-founder and chief technical officer at Synplicity. "In response to frequent requests from our customers, more than 30 percent of whom design both FPGAs and ASICs, we are now offering an ASIC synthesis solution which we expect will provide the same productivity benefits they have come to expect from Synplicity."

According to research from Collett International, the majority of today's ASIC designs is between 500,000 and one million gates and is implemented in 0.18 micron or higher process geometries. Along with its customers and ASIC Synthesis Advisory Panel members, Synplicity identified several barriers these designers face in achieving productivity in ASIC synthesis, including: the need for extensive scripting, long runtimes which limit the number of iterations per day; mismatches between synthesis and physical design hierarchies which impede timing closure; unpredictable behavior of tools; and long training time needed to begin using a synthesis tool. With the Synplify ASIC product, Synplicity seeks to remove these barriers and to deliver an order-of-magnitude improvement in designer productivity.

Dave Roth, director of ASIC development at Allegro Networks, a developer of router technology for enhanced network capability, said, "We were skeptical that a new synthesis tool could generate great results in a fraction of the time; the Synplify ASIC software has proven us wrong!"

The Synplify ASIC software is driven by Synplicity's core synthesis technology, the proprietary Behavior Extracting Synthesis Technology(R) (B.E.S.T.(TM)) algorithms and Synthesis Constraint Optimization Environment(R) (SCOPE(R)). Using this technology, the Synplify ASIC software enables the rapid synthesis of an ASIC design -- up to 15 times faster than traditional synthesis products -- with high quality of results. The software features a fast and accurate incremental timing engine for timing-critical designs and offers designers the flexibility to use either a command line interface for TCL scripting or an intuitive graphical user interface that simplifies the design process. The software also features Synplicity's popular HDL Analyst(R) RTL graphical analysis tool to ease the debugging process.

Vince Hopkin, Vice President, Conversion ASIC Business Unit, AMI Semiconductor, said, "AMI Semiconductor has made Synplicity's Synplify ASIC product the recommended FPGA-to-ASIC synthesis tool for our customers because it directly addresses our customers' most compelling design and time-to-market needs by generating excellent results in the shortest time possible."

With the introduction of the Synplify ASIC product, Synplicity offers a path from a single RTL design file to an FPGA, multiple FPGAs or an ASIC. In addition, many ASIC designers today use programmable logic to test all or part of their designs before committing the design to ASIC production. For these customers, many of whom currently use Synplicity(R) technology, the Synplify ASIC product can quickly re-target single-FPGA Synplify(R) and multi-FPGA Certify(TM) project files to an ASIC vendor implementation with a few mouse-clicks. Combined with the fast runtimes of the Synplify ASIC software, this capability creates a fast path for conversion of FPGA designs into ASIC implementations.

The Synplify ASIC Software: Users Become Proficient in a Day

Leveraging its core synthesis algorithms, Synplicity has helped to reduce or eliminate the need for the complex scripts and commands normally associated with synthesis products, enabling designers to focus on improving their designs rather than on manipulating their synthesis tool. In automating the synthesis process, Synplicity has created an easy-to-learn and easy-to-use ASIC synthesis solution. As a result, Synplicity believes it is possible for designers to become proficient users of the software in a single day, compared to weeks or months for current synthesis products.