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PMC-Sierra's OC-192 SONET/SDH Chip Set Enables Consolidation of Metro Optical Networks

Business Wire, March 19, 2001

Business Editors, Technology Writers

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BURNABY, British Columbia--(BUSINESS WIRE)--March 19, 2001

CHESS-II(TM) SONET/SDH Channelization Chip Set Creates New

Sub-Wavelength Optical Equipment To Replace Racks of Traditional

Equipment With a Single Shelf

PMC-Sierra (Nasdaq:PMCS) today introduced an OC-192/STM-64 line rate optical networking architecture that enables Internet Service Providers (ISPs) and telecommunication carriers to deliver voice, video and data services across a single optical transport backbone. Targeted at Broadband Internet Infrastructure equipment for the emerging Metropolitan Area Networks (MAN), PMC-Sierra's CHESS-II(TM) (Channelizer Engine for SONET/SDH) chip set enables optical transport functionality, sub-wavelength cross-connection and network service aggregation (see figure 1).

The CHESS-II chip set includes the PM5317 SPECTRA(TM)-9953 (STS-1 Channelized framer and pointer processor), PM5307 TBS-9953 (groomer and serializer), PM5374 TSE-160 (160 Gbit/s STS-1 cross-connect) and the PM5395 CRSU-4x2488 (4xOC-48 clock and data recovery). The CHESS-II chip set's unique architecture enables consolidation of traditional SONET/SDH equipment (SONET/SDH Add/Drop Multiplexers [ADMs], Terminal Multiplexers and Broadband Digital Cross-Connects), together with IP routers and multi service switches into a single shelf platform.

Networks are now being architected with new metro equipment such as Multi Service Provisioning Platforms (MSPPs) and sub-wavelength optical cross-connects which are enabled by CHESS-II (see figure 2).

The Metropolitan Transport Network Bottleneck

With network access services expanding rapidly, metropolitan transport networks have become the bottleneck. Today's SONET/SDH networks were originally designed to carry voice traffic and are unable to handle the proliferation of data and other services brought on by the emergence of the Internet. In response, carriers and ISPs must upgrade existing metro infrastructure to maintain and grow their service provisioning businesses. CHESS-II enables multiple platforms for data, voice and video services to be collapsed into a single network platform, reducing interoperability and scalability challenges.

CHESS-II: Improved Performance for Metro Area Networks

The CHESS-II chip set helps remove MAN bottlenecks by aggregating services such as Gigabit Ethernet, Internet Protocol, Fiber Channel and ATM into highly scalable SONET/SDH platforms exhibiting sub-wavelength cross-connect capabilities. Services in the MAN are initially aggregated into pipes at STS-1 (51.84 Mbit/s) level granularities. The CHESS-II chip set grooms these STS-1 pipes in such a way that multiple services can be transported over individual OC-192/STM-64 wavelengths or multiple OC-48/STM-16 wavelengths. This capability enables carriers to manage and direct services through the MAN in a more efficient manner.

"Metropolitan Area Networks bridge the space between long haul and access networks, aggregating lower rate clients into higher speed OC-48 and OC-192 trunks," said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division. "PMC-Sierra's CHESS-II chipset offers a complete metro solution allowing next generation carrier-class metro networks to offer increased service-level provisioning to users at lower cost by mapping multiple client services onto individual WDM/DWDM wavelengths," Perna continued.

CHESS II: Improved Density, Power and Scalability for Metro Area Networks

CHESS-II devices provide unprecedented density, lower power and scalability, enabling metro optical equipment to support more than 640 Gbit/s in a single shelf. The SPECTRA-9953, the industry's highest integrated channelized physical layer device for OC-192 and 4 port OC-48 applications, provides STS-1 channelization and path monitoring. The TBS-9953 provides working, protect and auxiliary high speed interfaces for sending 20 Gbit/s of data across high speed electrical and optical backplanes. PMC-Sierra's TSE-160 device integrates 64 bi-directional 2.5 Gbits/ interfaces for cross-connecting services with SONET/SDH granularities as fine as STS-1 (51.84 Mbit/s) to wavelengths as fast as an OC-768/STM-256. CHESS-II also provides the industry's highest density quad and lowest jitter OC-48 clock and data recovery solution with the CRSU-4x2488 exceeding ITU and Bellcore compliant jitter specifications for WAN compliancy.

The CHESS-II chip set is backplane and software compatible with the original CHESS chipset, allowing PMC-Sierra's wide customer base an easy migration path to highly integrated OC-192/STM-64 port cards. For more information about the CHESS-II devices, please refer to the table below and the attached technical overview.


Pricing, Packaging and Availability
                                                       Pricing  Sample
   Device         Features     Package     Process      in 1KU  Avail.
   ------         --------    ---------    -------     -------  ------
SPECTRA-9953  -- OC-192/     1152 FCBGA  0.18(mu) CMOS  $1175 Q3, 2001
  (PM5317)       OC-192c/STM-64,
                 4xOC-48/STM-16 SONET/SDH
                 FRAMER
              -- STS-1, AU3
                 channelization
----------------------------------------------------------------------
CRSU-4x2488   -- 4xOC-48      580 UBGA   0.18(mu) CMOS  $399 Q3, 2001
(PM5395)         Clock and Data
                 Recovery, Clock
                 Synthesis Unit
                 and Serial to
                 Parallel
                 converter
----------------------------------------------------------------------
TBS-9953
TelecomBus    -- 20 Gbit/s   1152 FCBGA  0.18(mu) CMOS  $469  Q3, 2001
Serializer       Working and
(PM5307)         Protect
              -- Parallel
                 TelecomBus to
                 Serial Backplane
                 LVDS at
                 2.488 Gbit/s
----------------------------------------------------------------------
TSE-160:      -- 16x16       1152 FCBGA  0.18(mu) CMOS  $1329 Q3, 2001
Transmission     OC-192 cross-connect
Switch        -- 160 Gbit/s
Element          aggregate
(PM5374)         bandwidth
              -- 3072 channel
                 STS-1
                 grooming
----------------------------------------------------------------------

--  All devices are characterized for industrial temperature range
    (-40(Degree)C to 85(Degree)C)

 

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