Cadence SP&R Design Technology Used by Advanced Hardware Architectures to Design 10-Million-Gate Hierarchical Chip

Business Wire, Nov 15, 2001

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 15, 2001

AHA Depends on 64-Bit Cadence Synthesis/Place-and-Route

Flow to Meet Tight Timing and Area Goals

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced that Advanced Hardware Architectures' (AHA) Fiber Division has designed and taped-out a 10-million gate Forward Error Correction (FEC) digital integrated circuit (IC) using the 64-bit Cadence(R) SP&R (synthesis/place-and-route) design flow. To design the 200 MHz FEC, dubbed "Project Neptune," on UMC's (NYSE:UMC) 0.18-micron process technology, AHA used Silicon Ensemble-(R) PKS (SE-PKS) optimization place-and-route solution from RTL to GDSII, including full-chip, post-route timing analysis in less than one hour.

"We have demonstrated that Cadence 64-bit SP&R technology can handle very large designs and mitigate the risk of missing goals," said Tim Heldt, staff EDA engineer, whose 10-million gate, 200-MHz chip was the largest designed and taped-out by AHA.

Jeff Hannon, Neptune's project manager, further reinforced this position by saying, "Cadence SP&R is a powerful flow. Hundreds of designers would typically work 18 months on a chip of this magnitude, yet we met our timing and area goals in 12 months with a staff of about 20 designers, many of whom were not on the project full time."

AHA specializes in the design of chips that embody its proprietary error-detection and correction algorithms for communications applications. The "Project Neptune" design represents the third chip that AHA's Fiber Division has successfully designed and taped-out this year using Cadence SP&R design technology. The two prior SP&R designs -- a 400-thousand-gate and a 2.5-million-gate design -- resulted in successful first silicon.

Project Neptune Design Flow

Because of "Project Neptune's" need for large capacity, AHA used a hierarchical physical design methodology in the SP&R flow leveraging the full complement of powerful and comprehensive technology engines in SE-PKS. AHA's SE-PKS design flow included:

-- Initial floorplanning

-- Synthesis of all blocks for timing convergent, global-routed block placement


-- Testability using pivotal scan insertion and placement-based scan chain
reordering

-- Datapath-intensive block area reduction and performance optimization

-- Optimization at the top-level with abstracted blocks and global-routed
timing convergence with world-class routing engine in SE-PKS

-- Final detail routing of all levels in the design hierarchy

-- Full-chip static timing analysis and final timing sign-off with integrated
timing engine

"We are delighted with AHA's repeated tape-out success using the Cadence SP&R flow," said John Murphy, vice president, Cadence SP&R. "The sheer size and complexity of 'Project Neptune' and its success is a testament to the capability of AHA's design team, and is another example of the superior capacity, performance, and quality of results achieved with SP&R."

About Cadence SP&R

Cadence SP&R is the industry's first unified synthesis/place-and-route system. It consists of Physically Knowledgeable Synthesis (PKS) and Silicon Ensemble-PKS optimization place-and-route. SP&R features correlation within three percent through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

Pricing and Availability

Cadence PKS and SE-PKS are available for UNIX-based workstations from Hewlett-Packard and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list prices start at $100,000 and $400,000, respectively. For information on international pricing, please contact a local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design products, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.

Note to Editors: Cadence, and the Cadence logo, and Silicon Ensemble are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.