STMicroelectronics Unveils Advanced CMOS and Non-Volatile Memory Developments at IEDM

Business Wire, Dec 5, 2002

Business & Technology Editors

IEDM 2002

GENEVA, Switzerland--(BUSINESS WIRE)--Dec. 5, 2002

STMicroelectronics (NYSE: STM), the world's third largest supplier of semiconductor devices, will present six papers at the IEDM 2002 (International Electron Devices Meeting) Conference, which takes place during December 8-11 in San Francisco, California.

During the conference, ST researchers will present four state-of-the-art innovations for future generations of CMOS technology and two papers devoted to advanced Non-Volatile Memory technology.

In the field of Flash memories, researchers from ST's R&D facility in Agrate, Italy, will present their study of the impact of P/E (Program/Erase) cycling and hot-carrier injection on tunnel oxide degradation and address the impact of program disturbs on the generation rate of the traps responsible for the phenomena of low temperature charge loss.

The second paper by Agrate researchers reports a detailed investigation of the electronic switching effects in chalcogenide-based phase-change devices (Ovonic Unified Memory - OUM). The electronic switching is the distinctive - and, till now, not yet fully understood - behaviour of this new type of memory device, which ST believes to be the best candidate to complement and eventually replace Flash memory for its superior performance and better scalability. Starting from a band-gap model of both crystalline and amorphous chalcogenide, a numerical model is proposed that accounts for both the DC and transient I-V device characteristics.

Three papers present advances in CMOS Technology achieved by ST and its research partners at the Crolles Central R&D facility at Crolles, near Grenoble, France.

High-k gate dielectric materials such as hafnium dioxide (HfO2) will be required in future CMOS generations and a team from ST, France Telecom R&D, CEA-LETI and Philips Semiconductors will describe 40nm n-channel MOSFETs featuring polysilicon gates and HfO2 gate dielectric. The performances obtained were similar to those of transistors built using conventional SiO2 dielectric but exhibited leakage currents around 100 times smaller - the highest performance ever reported for pure HfO2 with a polysilicon gate.

The Silicon-on-Nothing (SON) transistor architecture conceived by ST and its research partners France Telecom R&D and CEA-LETI allows extremely thin buried dielectrics and silicon films, no more than a few nanometers thick, to be fabricated with high accuracy within the methodologies of conventional epitaxial technology. This characteristic positions it as a leading candidate for future system-on-chip (SoC) technology. At IEDM, ST and its partners will describe the world's first SON transistors with totally silicided gates. Measurements on a PMOS transistor with a 55nm silicided metal gate and a very thin (5nm) silicon conduction channel showed excellent performance, including off-state current reduced by orders of magnitude compared with polysilicon gates.

ST and another group of research partners will also describe and characterize the world's first NMOS and PMOS transistor integration using a Damascene CVD TiN/W metal gate and a hafnium dioxide high-k dielectric. Key features of the new process include low off-state and gate currents that make it particularly promising for applications that demand low standby power consumption.

As CMOS devices are downscaled, more sophisticated models are required to take account of new effects introduced by the smaller dimensions. ST will also present an innovative approach in which existing simulation models have been extended to account for mechanical stress effects. These models are used in the design kit, allowing precise predictions closely matching circuit measurements.

"These papers underline both the excellence of our Crolles and Agrate centers and the strength of the long-term research partnerships we have established. They are a further demonstration that ST's unwavering commitment to R&D, even during the toughest industry downturns, continues to pay dividends, placing us at the forefront of CMOS and non-volatile memory technology development," said Joel Monnier, Corporate Vice President and Central R&D Director at STMicroelectronics.

Notes for Editors

(1) The Crolles center is the major hub for the development of the mainstream CMOS Technology Platforms, currently focused on the 90nm and 65nm generations. The Crolles facilities are organized as integrated facilities with R&D, pilot production and volume manufacturing all carried out using 200mm (Crolles1) or 300mm (Crolles2) wafers and all closely coupled to ensure optimum overall efficiency. Crolles also hosts joint teams between ST, Philips Semiconductors, Motorola and TSMC, with researchers from France Telecom R&D and CEA-LETI, working on advanced technology to prepare future CMOS platforms.

(2) The R&D Agrate center, Italy, is dedicated to the development and advanced manufacturing of products based on deep submicron Flash and other non-volatile memory technologies such as EPROM, EEPROM and smart cards. Like the Crolles centers, Agrate R2 is a fully integrated facility including a 200mm volume production fab.