Green Hills Software Announces MULTI Integrated Development Environment And Optimizing Compiler For MSC8102 at Smart Networks Developer Forum

Business Wire, July 22, 2002

Business Editors/High-Tech Writers

Smart Networks Developer Forum

Booth #301

NEW ORLEANS--(BUSINESS WIRE)--July 22, 2002

Green Hills Software Inc. today announced the availability of its MULTI(R) 2000 Integrated Development Environment and high-speed Green Hills Probe for the StarCore(R)-based MSC8102 digital signal processor, Motorola's highest performance DSP.

The new IDE, featuring C and C optimizing compilers and a multi-core debugger, provides a DSP-optimized superset of MULTI's powerful editing, debugging, profiling and project management capabilities. Green Hills Software will demonstrate the new IDE and probe running on an MSC8102 development board at the Smart Networks Developer Forum.

"Software developers are creating an increasing number of C and C applications on multi-core architectures such as the MSC8102," said John Carbone, vice president of marketing at Green Hills Software. "MULTI's ability to monitor and control multiple cores, both independently and synchronously, greatly simplifies software development for these complex multiprocessor systems. At the same time, our compilers enable MSC8102 developers to take full advantage of the MSC8102's powerful multi-core processing capabilities."

"The MSC8102's multi-core architecture presents unique opportunities and challenges for designers of high-performance telecommunications equipment," said Lynelle McKay, general manager of Motorola's Wireless Infrastructure Systems Division. "MULTI's advanced development, debugging and simulation facilities make it easy for customers to create and deploy efficient embedded applications that realize the full potential of our multi-core processors."

The MSC8102 combines four StarCore SC140 cores running at speeds of up to 300 MHz with four Enhanced Filter Coprocessors (EFCOPs), delivering a peak performance of 6000 million multiply accumulates per second (MMACs). This high performance level, coupled with the MSC8102's large on-chip memory (1436 Kbytes), four high-speed TDM interfaces, 16-channel DMA, and high performance system and peripheral bus interface, make it ideal for a wide range of compute-intensive telecommunications applications.

The MULTI 2000 IDE automates all aspects of software development for the MSC8102. Optimized for the MSC8102's SC140 core architecture, the MULTI IDE features a window-oriented editor, RTOS-aware, multi-core source-level debugger, graphical program builder, run-time error checker, version control system and performance profiler. MULTI also supports Motorola's StarCore instruction set simulator and multi-core cycle-accurate simulator, which enable programmers to develop and test MSC8102 code on a PC or workstation without the need for the target hardware.

The MULTI debugger, which supports incremental debugging, provides a separate window for each SC140 core and process, supports mixed assembly and high-level language formats and includes a language-sensitive expression evaluator. Using MULTI, MSC8102 programmers can simultaneously view all MSC8102 registers and debug all four SC140 cores, independently or synchronously setting hardware breakpoints, running, stepping or halting all four cores. The debugger also provides advanced trace capabilities, featuring trace analysis and trigger windows that make it easy for MSC8102 users to save and load trace data to files, identify pertinent exception events, initiate trace (before, after and during trigger events) and save/load trigger setups.

The MULTI debugger is RTOS aware, enabling users to debug and tune MSC8102 applications running under popular RTOSes such as OSE Systems' OSEck at a process level. With MULTI's freeze mode debugging, users can debug (including setting task-specific breakpoints) one or more processes running on any of the MSC8102 cores. MULTI communicates with the MSC8102 target system through either a Macraigor Wiggler, or Green Hills Software's own high-speed hardware debug Probe, which supports simultaneous multi-core debug with download rates of greater than 400 kbytes/sec.

MULTI features the industry's fastest and most efficient MSC8102 optimizing C and C compilers, which automatically partition code for optimal execution on the MSC8102's multiple MAC, ALU and BFU processing units. The compilers also take full advantage of the MSC8102's variable-length execution set (VLES), providing more than 100 advanced optimizations that boost performance and code efficiency. Reordering VLES instruction groupings, for example, boosts performance and reduces RAM usage by increasing VLES packing efficiency and increasing parallelism. The compiler also increases parallelism by reordering operations within loops, and reduces looping overhead by supporting zero-overhead hardware looping for loops that are nested up to four deep.

The MULTI IDE runs on Windows, Linux and Solaris hosts and will be available for the StarCore MSC8102 late in the third quarter of this year. MULTI pricing for Windows and Linux hosts starts at $5,900 (U.S.). MULTI for Solaris, and HP-UX starts at $9,900 (U.S.).