LISATek Paper Chosen As A `Best Paper' at 39th Design Automation Conference

Business Wire, June 5, 2002

Business Editors, Hi-Tech Writers

MENLO PARK, Calif.--(BUSINESS WIRE)--June 5, 2002

Technologists from LISATek and their Colleagues from the Aachen

University of Technology Win Best Paper Award in Embedded Systems

Category

LISATek(R), a company revolutionizing the design of embedded processors for system-on-chip (SoC) solutions, announced that a paper co-authored by LISATek technologists and their colleagues at the Aachen University of Technology, Germany, has been selected as the Best Paper in the Embedded Systems Category by the Technical Committee of the 39th Design Automation Conference (DAC).

The authors will be honored during the DAC General Session, slated for Tuesday, June 11, from 8:30 a.m. to 10:15 a.m., during DAC at the Ernest N. Morial Convention Center, in New Orleans, La.

The paper, titled "A Universal Technique for Fast and Flexible Instruction-set Architecture Simulation," was chosen from 491 papers submitted for the DAC technical conference. It is among three that will receive awards, and was the only paper chosen in the Embedded Systems Category. The paper will be presented by its authors to DAC conference attendees in room 288 of the Convention Center on Tuesday, June 11, from 10:30 a.m. to 12:00 noon.

The principal author of the paper was Achim Nohl, corporate applications engineer, LISATek; along with co-authors Andreas Hoffmann of LISATek; Gunnar Braun, Oliver Schliebusch, and professor Rainer Leupers of the Institute for Integrated Signal Processing Systems (ISS) at Aachen University of Technology; and professor Heinrich Meyr, LISATek Chairman of the Board and head of the ISS at Aachen University of Technology.

"Our paper addresses a revolutionary instruction-set simulation technique, called just-in-time cache compiled simulation (JIT-CCS)," said Meyr. "The technique combines the performance of traditional compiled simulators with the flexibility of interpretive simulation, which has been shown to be highly applicable to real-world architectures."

"We are proud that this paper has received this honor from the DAC Technical Committee, and we thank the Committee for recognizing the efforts of the team that authored it," said Uri Mayer, LISATek CEO. "JIT-CCS is just one of the ways LISATek is transforming the design of embedded processors for systems-on-chips (SoCs), making the process faster than ever before possible."

About LISATek

LISATek is a privately held electronic design automation (EDA) company founded in 2001. Its products are based on technology developed at Aachen University of Technology, Germany. The company offers a revolutionary platform for the design of embedded processors for system-on-chip (SoC) solutions. LISATek's instruction set simulator, JIT-CC(TM), is the fastest available today. Its unified tool suite, comprised of the EDGE(TM) Processor Designer, HUB(TM) System Integrator, and RIM(TM) Software Designer, is a complete solution that automatically generates all necessary tools for embedded processor design, embedded software development and for the integration and verification of embedded processors within a system-on-chip (SoC) environment. LISATek tools, software and hardware descriptions can now be based on a single specification, dramatically improving embedded processor design productivity for processor, SoC, and software designers.

For more information, visit http://www.lisatek.com or contact LISATek Inc. at 190 Sand Hill Circle, Menlo Park, Calif. 94025 U.S.A., telephone (650) 233-4344 or by email at info@lisatek.com. LISATek GmbH can be reached at Technologiezentrum am Europaplatz, Dennewartstrasse 25-27, 52068 Aachen, Germany; by telephone at 49 241 9631510; or by fax at 49 241 9631519.

Note: LISATek is a registered trademark and EDGE, HUB, RIM, and JIT-CC are trademarks of LISATek. All other trademarks are property of their respective owners.