Cypress Announces Industry's First Search Supervisory Coprocessor, Providing Comprehensive Search-System Management

Business Wire, Oct 14, 2002

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Oct. 14, 2002

Vichara(TM) 81000 Coprocessor Aggregates Searches from Multiple

Packet Processors; Up to 40 Gbps of Throughput Enables Wirespeed

Packet Processing

Cypress Semiconductor Corporation (NYSE:CY), today introduced Vichara(TM) 81000, the industry's first Search Supervisory Coprocessor. The Vichara coprocessor enables packet processors to achieve 40 Gbps throughput by offloading search-intensive processing and managing multiple searches. It maximizes look-aside (LA-1) bus bandwidth and simplifies overall search-system management. When used in conjunction with Cypress's Ayama(TM) NSE10000 family of network search engines (NSEs), the Vichara 81000 enables as many as 266 million searches per second (MSPS).

The Vichara 81000 relieves network processors (NPUs) and application specific integrated circuits (ASICs) of routing lookups and policy-resolution functions. By offloading these search-related instructions, the Vichara 81000 increases the packet processor's ability to perform other linecard functions, resulting in more processor headroom. It also relieves packet processors of control-function management by providing direct connectivity and hardware features to perform out-of-band control updates for policing and aging functions, enabling the NPU/ASIC to process more packets per second at the same wirespeed.

"Complexity of the linecard search subsystem is increasing with the advent of services such as quality of service (QoS), policy and billing," said Jag Bolaria, senior analyst at the Linley Group and co-author of A Guide to Classification and Traffic Management Coprocessors. "All of these advanced features involve multiple lookups per packet, varied searches and the sharing of databases by multiple processors. At 2.5 Gbps and beyond, packet processors are struggling to maintain throughput and meet the requirements for these services. Cypress is the first to address this problem using its search supervisory coprocessor. The Vichara coprocessor offloads search instructions and data from the packet processors to minimize the search complexity while providing significant processing headroom. There's no other product on the market today that has solved this issue so elegantly."

"The increasingly complex nature of policy- and forwarding-based searches has created an urgent need for a highly intelligent solution to manage and coordinate searches in a subsystem that could contain multiple processors, NSEs and memory," said Christopher Norris, vice president of Cypress's Data Communications Division. "The Vichara 81000 enables the next generation of packet processing by acting as a central controller in the search subsystem and providing the NPUs and ASICs with the bandwidth to achieve their full potential."

The Need for Speed

Current data-plane packet processors (NPUs or ASICs) perform parsing, routing, policy resolution, modification and scheduling of packets on the linecard. In addition, the control processor concurrently performs control updates in-band through the packet processors on the data path. As wirespeed increases from 2.5 Gbps to 40 Gbps, these processors are unable to perform all the functions without additional assistance. The problem is aggravated by an increased need for policy enforcement to provision higher layer services and deeper network tables to handle the growing number of devices on the Internet. The Vichara 81000 coprocessor helps alleviate this problem.

Designed to supervise the search sub-system on the linecard, the Vichara 81000 connects seamlessly with the packet processor through the LA-1 bus; with NSEs and NoBL SRAMs through their native buses; and with a control processor through the PCI bus interface (see block diagram at http://www.cypress.com/pub/vichara1.jpg). After downloading the packet data and search instructions from the packet processor, the coprocessor manages the search system consisting of NSEs and SRAMs. With its unique search management capabilities of conditional branching and recursive search features, the Vichara 81000 is able to coordinate the execution of multiple classes of lookups (for example, access control lists, forwarding and QoS lookups) across multiple contexts from multiple packet processors, returning only the final results to the processors.

Having a search supervisory coprocessor also simplifies hardware and software design for the linecard since the designer can fine-tune the search-system performance through a full suite of Vichara 81000 hardware features and software. In addition to simpler hardware and software design for search systems, the coprocessor's unique search management system translates to wider and deeper search tables, since multiple NSEs and SRAMs can be cascaded to Vichara.

The Vichara 81000 solves the LA-1 bus bottleneck by offloading search management from the packet processors. Due to its narrow width -- 18 bits (including two parity bits) -- the standard LA-1 bus faces severe congestion resulting from multiple lookups per packet required to process each packet. For a typical Packet over SONET (POS) application, congestion can run as high at 95% at 10 Gbps for lookup functions only. Since the same LA-1 bus is used for other SRAM-related functions, this high bus congestion can ultimately increase system latency significantly. By aggregating search instructions and related data from the processor side of the LA-1 bus and running them on the NSE/SRAM side, Vichara drastically reduces the LA-1 bus congestion (down to 24% from 95% for the POS application referenced above). Reduced bus congestion means lower search latency and use of fewer Packet processor LA-1 ports for search processing.