Tera Systems Technology Helps Extend IBM ASIC Methodology To Midrange Applications

Business Wire, April 2, 2003

Business Editors/High-Tech Writers

CAMPBELL, Calif.--(BUSINESS WIRE)--April 2, 2003

Tera Systems' TeraForm(R) RTL SVP to Provide Simplified Front-End

Chip Design Tool That Reduces Customer Time, Cost

and Expertise Required to Generate Complex ASIC Designs

Tera Systems, Inc., today announced that TeraForm RTL Silicon Virtual Prototype (SVP) has been integrated into the IBM Blue Logic(R) MidRange ASIC design flow. IBM and Tera jointly developed and qualified this flow in support of a new engagement model allowing RTL handoff of customer designs. This model will enable greater focus on functional design by system design customers while leveraging IBM's extensive design implementation tool suite and design center expertise.

IBM offers their customers extensive ASIC design experience and capabilities, accumulated over two decades, including a comprehensive suite of intellectual property, systems architecture skills, and proven design implementation tools and methodologies for system-on-chip (SoC) designs. "In the past, IBM has focused on the high end of the ASICs market. With this new methodology, we are expanding our focus beyond high-end applications," said Tom Reeves, vice president of ASICs, IBM Microelectronics Division. "We're capitalizing on our leadership position in advanced technologies and extensive design capabilities. Through our joint work with Tera, we are now delivering this new methodology to customers who want the security of working with IBM on mid-range designs with an RTL handoff-based flow."

TeraForm is used on customer designs upstream from synthesis to identify potential timing, area, congestion and design-closure issues early in the design cycle at the RT-level. This leads to better predictability and shorter time-to-market. The TeraForm-IBM flow delivers predictive analysis allowing early visibility into issues like critical-path timing violations and routing congestion while the RTL is being written, alleviating time-consuming late-stage design iterations.

TeraForm identifies and resolves a wide variety of design implementation issues that can only be corrected in RTL. By identifying these problems up front in the design flow, at the earliest stages of RTL completion, designers can avoid major issues preventing design closure that are typically found during gate-level implementation. The reduction in time to final design closure enhances schedule predictability and increases the overall quality of the ASIC.

"IBM's new ASIC design flow with Tera Systems' TeraForm allows customers to increase their focus on functional design, architectural refinement, and resolution of system-level issues instead of low-level design implementation and debug problems," said Alain Labat, president and CEO at Tera Systems, Inc. "By leveraging IBM's experience along with TeraForm's SVP technology, our joint customers will be able to gain the competitive advantage, creating a mission critical 'win/win' through enhanced design predictability."

About Tera Systems

Tera Systems, Inc. is the leader in RTL silicon virtual prototype technologies for use by designers of complex system-on-chip (SoC) semiconductors. The company's products provide early visibility into design quality, performance and manufacturability issues with the goal of preventing downstream problems with synthesis and physical design processes. For more information, visit our web site at www.terasystems.com

Note to Editors: TeraForm and TeraGate are trademarks of Tera Systems. All other trademarks are the property of their respective owners.