QuickLogic Announces Eclipse-II, Industry's Lowest-Power FPGA Family

Business Wire, Feb 3, 2003

Business Editors

SUNNYVALE, Calif.--(BUSINESS WIRE)--Feb. 3, 2003

QuickLogic Corporation (Nasdaq:QUIK)

-- High performance, feature-rich FPGA addresses the needs of CPLD and ASIC designers

-- Small form factor, single chip solution saves board space

-- Highest design security against reverse engineering and IP piracy

QuickLogic Corporation (Nasdaq:QUIK), the pioneer of ESPs (embedded standard products), today announced the availability of the Eclipse-II FPGA family to address applications that demand ultra-low power, small form factor packaging, and high design security. Eclipse-II FPGAs exceed the functionality previously addressed by Complex Programmable Logic Devices (CPLDs) and FPGA devices while providing significant power and cost savings. With an architecture that features dedicated SRAM blocks, flexible clock architecture and ultra-low power consumption, the Eclipse-II family offers FPGA, CPLD, and ASIC designers multiple solutions for their applications.

"Our patented ViaLink(R) interconnect technology enables QuickLogic to deliver the lowest power, most routable FPGA in the industry," said Brian Faith, QuickLogic's Manager of FPGA products. "The low power architecture of Eclipse-II provides developers of mobile, portable, wireless, and hand-held systems with a feature-rich alternative to CPLDs and ASICs. In addition, the low power consumption (i.e. 250 uA standby current) of Eclipse-II FPGAs enables designers to reduce system costs by using smaller, less costly voltage regulators and power sources.

The Eclipse-II family is available in small form factor packaging, giving system developers the benefits of a low power, high-performance FPGA without sacrificing board space. This packaging makes the devices ideal for miniaturized portable consumer products. Unlike some other FPGAs, the Eclipse-II devices do not require an external memory to retain the FPGA configuration data, thereby saving additional board space and power consumption. A single-chip solution means less board area, which in turn reduces end-system cost for designers.

Armed with QuickLogic's patented non-volatile ViaLink interconnect technology, Eclipse-II FPGAs provide exceptionally high levels of design security from reverse engineering and IP theft. Additional architectural features in the Eclipse-II FPGA family afford users the highest level of design security, above and beyond that of ASICs.

Flexible, High Performance Clock Architecture

One of the most difficult challenges in system design today is how the multitude of clock domains are distributed and managed. Towards this end, Eclipse-II devices are equipped with a large number of distributed clocks enabling designers to bridge up to 20 clock domains in a single Eclipse-II FPGA. In addition, the flexible clocks networks can drive user-programmable Phased Locked Loops (PLLs). These PLLs can be programmed for clock frequency multiplication, division and be used to improve your design's I/O performance. Eclipse-II PLLs not only reduce chip-to-chip delays in high performance systems, they also reduce the number of components on a designer's board, thus further reducing end-system costs.

Eclipse-II Applications

The Eclipse-II FPGA family addresses a wide range applications such as mobile, wireless, handheld, portable, medical equipment and defined form factors such as PCMCIA, CardBus, MiniPCI, and SDIO.

Software and Intellectual Property Support

QuickLogic provides designers with QuickWorks(TM) an intuitive, easy-to-use development environment including schematic entry, simulation, synthesis, accurate power calculation, timing driven placement and routing, and static timing analysis tools. The Eclipse-II FPGA family is supported in QuickWorks version 9.4, and is available now for download from www.quicklogic.com. QuickLogic offers several IP blocks for use in QuickLogic FPGAs such as PCI, memory interface, DSP and other commonly used functions.

Note: see related QuickLogic's QuickWorks V9.4 announcement today.

Pricing and Availability

The Eclipse-II FPGA family of devices start at $3.50 (for quantities of 250K or more.) The first device in the Eclipse II family will be sampling in early Q3, 2003. See the QuickLogic website for additional information on the Eclipse-II family: www.quicklogic.com

                                QL8025 QL8050  QL8150  QL8250  QL8325
                                ------ ------ ------- ------- -------

Max Gates                       47,052 63,840 188,946 248,160 320,640
                                ------ ------ ------- ------- -------
Logic Array                       16x8  16x16   32x20   40x24   48x32
                                ------ ------ ------- ------- -------
Logic Cells                        128    256     640     960   1,536
                                ------ ------ ------- ------- -------
Max Flip-Flops                     526    884   1,697   2,670   4,002
                                ------ ------ ------- ------- -------
Max I/O                             90    124     139     250     310
                                ------ ------ ------- ------- -------
RAM Modules                          4      4      16      20      24
                                ------ ------ ------- ------- -------
RAM bits                         9,216  9,216  36,864  46,100  55,300
                                ------ ------ ------- ------- -------
Embedded Computational Units         0      0       0      10      12
                                ------ ------ ------- ------- -------
Distributed Clocks                   5      5       5       9       9
                                ------ ------ ------- ------- -------
PLLs                                 0      0       0       4       4
                                ------ ------ ------- ------- -------
Packages (pins)

 VQFP                              100    100     100
                                ------ ------ -------
 CS BGA (0.8 mm)                   196    196     196
                                ------ ------ -------
 PQFP                              208    208     208     208     208
                                ------ ------ ------- ------- -------
 FBGA (0.8 mm)                                            280     280
                                                      ------- -------
 BGA (1.0 mm)                                             484     484
                                                      ------- -------