Atmel's mAgic Complex Domain DSP Soft Core Delivers 1.0 GFLOPS At 100 MHz

Business Wire, June 23, 2003

Business Editors/High-Tech Writers

COLORADO SPRINGS, Colo.--(BUSINESS WIRE)--June 23, 2003

Floating-Point VLIW DSP Offers Single-cycle Execution of

FFTs and Complex MACs for Wave Processing Applications

Atmel(R) Corporation (Nasdaq:ATML) today introduced mAgic, the world's first complex domain, extended precision very long instruction word (VLIW) DSP core for SoC implementation. The mAgic core provides single-cycle execution of complex arithmetic operations, such as FFT butterflies and vector2 arithmetic. Complex arithmetic is used to execute differential calculations and adaptive beam forming algorithms that are used in high-quality hands free audio conferencing, physical modeling of musical instruments and the inner ear, spectrum analysis, audio encoding/decoding, missile guidance control, auto collision avoidance and radar applications. These applications typically require GFLOPS-plus throughput.

Traditionally, DSP makers respond to higher throughput requirements by increasing clock frequencies, which increases power consumption and heat dissipation. Atmel has taken the novel approach of creating a new DSP architecture that delivers GFLOPS-plus throughput at a low clock frequency, which dramatically simplifies SoC timing closure and reduces the need for pipelining. The mAgic DSP executes 15 operations per cycle in parallel, and, at only 100 MHz, delivers 1.5 billion operations per second (GOPS), of which 1 billion are floating point. The core's 40-bit precision provides a 32-bit mantissa (e.g. for high quality audio and matrix inversion stability) and an 8-bit exponent field. Competing GFLOPS-plus DSPs require more than twice the clock frequency of mAgic and consume three times more power. For example, the TMS320C67 requires 14,400 cycles and 3X the power to perform an FFT on 1024 elements, while the mAgic DSP requires only 5,962 cycles for the same calculation. (source: {Benchmarks : C67x(TM) DSP Benchmarks)

The mAgic VLIW DSP architecture is the result of 20 years of research conducted by Pier Stanislao Paolucci, mAgic architect and Permanent Researcher at the Italian National Institute of Nuclear Physics (INFN), and by key mAgic designers who participated in the Massively Parallel Processing Project (APE) VLIW architectures have massively parallel processing structures and long instruction words that allow multiple operations to be executed in a single instruction cycle. Atmel manufactures the VLIW ASICs designed for the TERAFLOPS systems of INFN. The mAgic DSP core is now being offered as a library element, usable by Atmel's other ASIC customers.

Floating Point DSP Offers Easy Code Development/Larger Dynamic Range and High Precision - Competing fixed-point DSPs require that the floating-point code developed in MATLAB be re-written in a fixed-point representation. The translation process is extremely time-consuming, often taking months. Fixed-point code can lead to computational errors (overflow and round-off) that can adversely affect system performance or even cause complete system failure. The floating-point mAgic processor completely eliminates these issues. Code is developed on a PC and ported directly to mAgic, maintaining identical system behavior.

Software Tools offer 2X to 3X Code Compression - mAgic comes with a visual, Modular Application Development Environment (MADE) that includes a high level macro-assembler/optimizer, GNU(TM) compilers, eCos(TM) RTOS, and a unified debugging environment. A cycle accurate simulator provides 5 KIPS operation and an instruction accurate simulator provides 2 MIPS simulation.

The mAgic macro-assembler optimizer uses Atmel's patent-pending code compression scheme that results in code density of only 4-bits per floating point arithmetic instruction for numerically intensive operations, and average effective code density of 50-bits per stored VLIW instruction cycle, without loss of performance. The high code density allows the mAgic's DSP to store 24,000 VLIW cycles on-chip without using external memory.

Simplified VLIW Code Development - The mAgic core is the only VLIW DSP on the market that eliminates the difficulty of writing long (e.g., 128-bit), highly parallel VLIW instructions. A macro-assembler optimizer in the mAgic assembler automatically analyzes the logical and temporal data dependencies in serially written code, and then schedules all operations to optimize both resource usage and pipeline depth. This process is entirely seamless and requires no explicit intervention on the part of the engineer. Other leading DSP makers do not offer this capability.

The mAgic instruction set is divided into four orthogonal groups that support RISC-like compilation technology. These include: 1) register to register arithmetic computation; 2) load/store memory to registers; 3) control flow and 4) multiple loading of immediate data values inside the processor.

Availability and SoC Implementation - Atmel's complex domain, floating point mAgic DSP core is available now for immediate SoC implementation. Atmel offers qualified customers a SoC Prototyping and Emulation Platform (PEP) board for immediate system prototyping, emulation and early code development. Optional implementations of the PEP board may include ARM(R) 7, ARM 9 and Atmel's own 8-bit AVR(R) core. The PEP board includes comprehensive memory subsystems, high speed SRAM, Flash, peripherals, and an FPGA (500K ASIC gates) for custom IP blocks. Atmel's SoC design methodology uses existing standard products as platforms for SoC development and prototyping, thereby reducing SoC development time to as little as three months. Atmel is one of the top ten ASIC suppliers in the world, offering standard cell implementations in the latest process technologies. Options include everything from full custom, turnkey to joint designs in CMOS, mixed signal, embedded nonvolatile, BiCMOS and SiGe technologies in Atmel's own fabs.