Atmel's mAgic Complex Domain DSP Soft Core Delivers 1.0 GFLOPS At 100 MHz

Business Wire, June 23, 2003

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Business Editors/High-Tech Writers

COLORADO SPRINGS, Colo.--(BUSINESS WIRE)--June 23, 2003

Floating-Point VLIW DSP Offers Single-cycle Execution of

FFTs and Complex MACs for Wave Processing Applications

Atmel(R) Corporation (Nasdaq:ATML) today introduced mAgic, the world's first complex domain, extended precision very long instruction word (VLIW) DSP core for SoC implementation. The mAgic core provides single-cycle execution of complex arithmetic operations, such as FFT butterflies and vector2 arithmetic. Complex arithmetic is used to execute differential calculations and adaptive beam forming algorithms that are used in high-quality hands free audio conferencing, physical modeling of musical instruments and the inner ear, spectrum analysis, audio encoding/decoding, missile guidance control, auto collision avoidance and radar applications. These applications typically require GFLOPS-plus throughput.

Traditionally, DSP makers respond to higher throughput requirements by increasing clock frequencies, which increases power consumption and heat dissipation. Atmel has taken the novel approach of creating a new DSP architecture that delivers GFLOPS-plus throughput at a low clock frequency, which dramatically simplifies SoC timing closure and reduces the need for pipelining. The mAgic DSP executes 15 operations per cycle in parallel, and, at only 100 MHz, delivers 1.5 billion operations per second (GOPS), of which 1 billion are floating point. The core's 40-bit precision provides a 32-bit mantissa (e.g. for high quality audio and matrix inversion stability) and an 8-bit exponent field. Competing GFLOPS-plus DSPs require more than twice the clock frequency of mAgic and consume three times more power. For example, the TMS320C67 requires 14,400 cycles and 3X the power to perform an FFT on 1024 elements, while the mAgic DSP requires only 5,962 cycles for the same calculation. (source: {Benchmarks : C67x(TM) DSP Benchmarks)

The mAgic VLIW DSP architecture is the result of 20 years of research conducted by Pier Stanislao Paolucci, mAgic architect and Permanent Researcher at the Italian National Institute of Nuclear Physics (INFN), and by key mAgic designers who participated in the Massively Parallel Processing Project (APE) VLIW architectures have massively parallel processing structures and long instruction words that allow multiple operations to be executed in a single instruction cycle. Atmel manufactures the VLIW ASICs designed for the TERAFLOPS systems of INFN. The mAgic DSP core is now being offered as a library element, usable by Atmel's other ASIC customers.