Mentor Graphics Catapult C Synthesis Proven to Create Optimized ASIC/FPGA Hardware from Untimed C++ Up to 20 Times Faster

Business Wire, May 31, 2004

Business Editors/High-Tech Writers

WILSONVILLE, Ore.--(BUSINESS WIRE)--May 31, 2004

Mentor Graphics Corporation (Nasdaq:MENT) today announced its Catapult(TM) C Synthesis product, the only algorithmic synthesis tool that uses pure, untimed C to create quality register transfer level (RTL) descriptions up to 20 times faster than traditional manual methods. With the Catapult C Synthesis tool, hardware designers can significantly reduce RTL implementation time, improve design flow reliability and shrink hardware size. The Catapult C Synthesis tool targets designers developing application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) for next-generation, compute-intensive applications such as wireless communication, satellite communication and video/image processing.

By uniting system-level and hardware design, the Catapult C Synthesis tool combines with the Mentor Graphics(R) ModelSim(R) simulator to create the central foundation for a C-based design flow.

"Mentor Graphics has been working closely with key electronics companies that are designing extremely complex devices to develop and prove the benefits of the Catapult C Synthesis tool. The results, in the form of more than 10 tapeouts, show these companies producing reliable hardware that is up to 50 percent smaller in size, in a significantly reduced amount of time," said Simon Bloch, general manager, design creation and synthesis division, Mentor Graphics. "Our Catapult C Synthesis tool will no doubt have a major impact on future C-based ASIC and FPGA design."

Today's complex and high-performance designs are quickly outgrowing manual RTL creation methods due to the time it takes to create and verify RTL circuit descriptions and to the numerous errors that can be introduced in the interpretation process from the original system-level specification. Additionally, time-consuming manual methods prohibit designers from fully exploring the micro-architecture and interface design space, leading to suboptimal designs in terms of area and speed. Clearly, first-generation behavioral and pseudo-timed approaches are not meeting designers' needs for fast, high-quality designs.

By raising the abstraction level and leveraging the same untimed C source typically generated by system designers, hardware designers can now automatically create a precise, repeatable path from C models to hardware much more quickly than conventional manual methods. With a single source, designers can create error-free flows that are reliable, repeatable, and reusable and that produce RTL descriptions specifically tuned to the RTL synthesis tool and vendor technology.

The Catapult C Synthesis tool is the only product to synthesize a C source where both the core algorithm and interface are untimed. As a result, designers can perform detailed "what-if" analysis on varying micro-architecture and interface scenarios achieving fully optimized hardware designs. The tool creates RTL that can be synthesized into gates using standard RTL synthesis products, such as Design Compiler for ASICs or Precision(R) RTL for FPGAs.

"Our ability to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption, speaks for itself," said Peter Nord, Project Leader EDA and Methodology Coordination, Ericsson Mobile Platforms. "The cooperation between Mentor Graphics and Ericsson to develop a C-based tool that meets our requirements has been fantastic."

Interface Synthesis and Library Builder Technologies Yield Key

Differentiation

Other high-level synthesis approaches "wrap" the untimed C algorithm in a timed interface, resulting in a pseudo-timed source that is hard-coded to the hardware interface. The Catapult C Synthesis tool contains a patent-pending synthesis technology that allows the untimed C source to remain completely independent of the hardware interface. With this innovative technology, designers can quickly analyze performance tradeoffs, for instance, between single-port versus dual-port memory. Rather than wasting silicon area, designers can use interface synthesis to exactly match the hardware resources to the available bandwidth of the target interface. Designers can also switch from one interface to another by simply changing the constraint in the intuitive user interface. As a result, the same source code can be used for multiple purposes such as a single-port memory, streaming data, or a complex advanced microcontroller bus architecture (AMBA) bus.

The foundation of a high-level synthesis tool is the ability to accurately model the critical metrics for the destination technology and RTL synthesis tool in order to allow efficient tradeoffs between varying micro-architectures. The Catapult C Synthesis tool uses the accompanying Catapult C Library Builder(TM) tool to collect detailed characterization data from the downstream RTL synthesis tools with specific target technology libraries. This allows the Catapult C Synthesis tool to precisely schedule hardware resources, and quickly provide accurate area, latency and throughput estimates without spending costly time and effort going through RTL synthesis. The end result is higher quality designs in less time. The Catapult C Library Builder tool also allows designers to leverage custom components including memories, intellectual property (IP), DesignWare and existing RTL.