Sequence to Host NanoCool Low Power Design Seminars in Japan and Korea; Artisan, Forte, Tensilica and Toshiba to Discuss Power-Aware Tools and Techniques

Business Wire, Nov 2, 2004

TOKYO -- Sequence Design, the accuracy and performance leader for power integrity tools, today announced the next two locations, Tokyo and Seoul, for its NanoCool seminars. Artisan Components, Inc. (Nasdaq:ARTI), Sun Microsystems and Forte Design Systems will sponsor the NanoCool Tokyo seminar on November 10, 2004. Speakers from the sponsoring companies, as well as Toshiba and Tensilica will explore logic and physical low-power design methodologies. Sequence will continue the series in Seoul, Korea, on November 12, 2004.

RTL power estimation, designing for power using behavioral synthesis and SystemC, voltage-drop analysis, power modeling, power grid design and leakage reduction will all be explored during the seminar. Kimiyoshi Usami, professor at the Shibaura Institute of Technology, will be the keynote speaker at the Tokyo seminar.

The NanoCool technology seminars will offer primers on how to apply methodologies. "These seminars will give designers an ESL to gate-level perspective on how to efficiently manage power," said Vic Kulkarni, president and CEO at Sequence Design. "Companies in Japan and Korea have been at the vanguard of low-power design. Under our NanoCool initiative, we have worked closely with Toshiba and Artisan to create advanced methodologies in areas such as leakage power reduction. Attendees will get a first hand view of a collaborative power integrity flow."

According to Neal Carney, Artisan's vice president of marketing, "To help designers overcome the complex nanometer design challenges and to gain greater confidence in meeting power and performance budgets, it's important to provide IP that supports various power reduction solutions and includes accurate power and signal-integrity modeling."

At 90 and 65 nanometers, power is becoming a 'first-order' effect. "The power problem is the No. 1 issue in the long-term for computing. It's time for us to stop making 6-mile-per-gallon gas guzzlers," said Greg Papadopoulos, chief technology officer with Sun Microsystems (SJ, Mercury News, 7/2/04).

Designers can have the greatest impact on reducing power at the 'front-end' of the design process. "The understanding and management of a design's power characteristics have never been more important," added Brett Cline, vice president of marketing at Forte. "By utilizing behavioral synthesis techniques with advanced power estimation and analysis, design teams will have a clearer understanding of how power will affect their design earlier in the design process when options are still available."

TOKYO AGENDA

9:30 A.M.   Registration

10:00 A.M.  Corporate Overview (Sequence)

10:15 A.M.  Keynote:
            Technology Directions of Leakage Power Reduction
            Presenter: Kimiyoshi Usami, Dr. Eng.
            Associate Professor of Shibaura Institute of Technology

11:00 A.M.  Low Power Design for Logic Designers at ESL and RTL
             (Sequence)

11:30 A.M.  Power tradeoff of RTL designs generated by behavioral
             synthesis (Forte Design Systems)

12:00 P.M.  Lunch

12:45 P.M.  Leakage Power Reduction through MTCMOS (Sequence)

1:30 P.M.   Selective-MT Technique for Leakage Current Reduction
             (Toshiba)

2:00 P.M.   Throttle Microprocessor Core Power Dissipation: Use RTL
             Power Analysis Early and Often (Tensilica)

2:30 P.M.   Break

2:45 P.M.   IP for low power (Artisan Components)

3:25 P.M.   Concurrent Analysis and Optimization for Power Integrity
             (Sequence)

4:05 P.M.   Q&A

The Challenges to Power Management

The earliest forms of low power design involved the basic practice of reducing the power supply voltage, either in the entire design or in certain parts. The attractiveness of this approach was, and still is, the quadratic relationship between the supply voltage and the resulting power consumption. An additional method involved the use of more advanced semiconductor processes with narrower transistors and shorter wires -- all else being equal, the reduction in parasitic capacitances due to the smaller geometries resulted in less dynamic power.

Today, these approaches are no longer enough and in some cases -- such as sub-threshold leakage -- counter productive.

"10X reductions in leakage can be achieved through the use of power gating techniques," said Jerry Frenkil, Sequence's chief technology officer.

"A designer can have the greatest impact on reducing power at the RTL level," said Tom Miller, vice president, power analysis products with Sequence. "Methodologies are now being explored at ESL as well for views at even higher levels of abstraction."

"Being able to run power analysis at RTL is very important because it allows us to get a handle on power consumption very early in the design process, and then make appropriate changes to reduce power," said Himanshu Sanghavi, hardware engineering manager, Tensilica. "By getting these insights at RTL, we can meet our power goal more efficiently. The time for a more comprehensive power integrity solution is now."