PMC-Sierra Unveils 1.8 GHz Dual CPU 64-Bit MIPS-Powered Multiprocessor; The RM11200, PMC-Sierra's Third Generation Multiprocessor, Adds New CPU Core, PCI Express and DDR2

Business Wire, Oct 4, 2004

SANTA CLARA, Calif. -- PMC-Sierra, Inc. (Nasdaq:PMCS) today announced its third generation highly integrated 64-bit MIPS-Powered(TM) multiprocessor at the Fall Processor Forum. Using both PMC-Sierra's proven System-on-Chip (SoC) platform design methodology and 90 nm CMOS process technology, the RM11200(TM) integrates two newly designed 1.8 GHz E11K(TM) CPU cores with multiple high-speed memory and I/O interfaces, including dual DDR2, dual PCI Express(TM), quad Gigabit Ethernet ports, and HyperTransport(TM) (see Figure 1). The RM11200 was designed to provide customers with the highest level of processing performance, low power and leading edge integration for high performance networking, storage and communications applications such as enterprise routers, storage systems and DSLAMs.

"PMC-Sierra has always been regarded as a master in delivering high operating frequency embedded processors, and they've done it once again with this new E11K core. Furthermore, PMC-Sierra has matched this 1.8GHz embedded processor core with peripherals designed to meet the needs of next generation embedded systems, including the DDR2-800," said Markus Levy, industry analyst and president of the Embedded Microprocessor Benchmarking Consortium (EEMBC). "The RM11200 will clearly be the MIPS-based performance leader."

"System designers face multiple challenges when developing high performance equipment, which include balancing the need for high I/O bandwidth, low memory latency, high processing performance and low power," said Steve Perna, vice president and general manager for the Microprocessor Products Division at PMC-Sierra. "The RM11200 uniquely addresses these critical challenges to provide our customers with optimal system performance and low power."

Next Generation Memory and I/O Deliver Ultra High Bandwidth

The RM11200 addresses the high bandwidth requirements for next generation networking, storage and communications equipment by providing multiple memory and I/O interfaces such as DDR2, PCI Express, Gigabit Ethernet and HyperTransport. The dual 64-bit DDR2 memory controllers support frequencies up to DDR2-800, and support 8-bit ECC. The PCI Express interfaces support either dual 4-lane interfaces or a single 8-lane interface. The quad Ethernet interfaces support automatic assignment into 8 queues per port and perform HW checksum assist. The HyperTransport interface runs up to 600 MHz link frequency, providing up to 10 Gbs of full duplex bandwidth. All of the I/O interfaces support Direct Deposit(TM), which allows external peripherals to write directly into the L2 cache, avoiding costly external memory accesses and greatly increases system performance.

E11K Cache Optimized for Performance and Reliability

Building on the proven performance of the E9K(TM) CPU, each E11K core quadruples the Icache to 64KB, doubles the Dcache to 32KB, and delivers a total of 1 MB of on-chip L2 cache, with ECC in both the L1 and L2 for maximum data reliability. The dual 7-stage, symmetric superscalar E11K cores support full hardware processor-to-processor cache coherency using the 5-state MOESI cache coherency protocol, as well as full hardware I/O coherency over each of the I/O interfaces.

Non-Blocking XBAR Provides High Bandwidth and Low Power

The XBAR connects the processor cores, memory and I/O interfaces together and can support an aggregate bandwidth of over 1 Tbit/s, with a very low 3 nsec port-to-port latency. The XBAR uses a clockless technology, which cuts power by eliminating the need for a global clock. As a result, power consumption in the XBAR is proportional to the amount of data the XBAR is switching (see block diagram, Figure 1).

Pricing, Availability and Customer Support

Initial samples of the RM11200 device will be available in Q2, 2005 with volume pricing estimated at $450. The RM11200 is fabricated in 90 nm CMOS process technology and is available in an 1152-pin Flip Chip BGA package. A comprehensive support product package including datasheets, application notes, reference design, and software is available. Please contact PMC-Sierra applications support for more information at apps@pmc-sierra.com or visit www.pmc-sierra.com/processors.> Three Generations of Highly Integrated Multiprocessors

The RM11200 multiprocessor expands PMC-Sierra's successful portfolio of highly integrated dual processor solutions, which includes the RM9000x2(TM) and RM9000x2GL(TM) (see Figure 2). Utilizing PMC-Sierra's proven SoC design methodology, the RM9000(TM) and RM11000(TM) families of dual- and single-core microprocessors provide the highest levels of processing power, high bandwidth I/O integration, and low power required for high performance networking, storage, industrial control, laser printers, and high-end consumer applications. The RM11200 is 100% compatible to the MIPS Instruction Set. For more information on the RM9150(TM), RM9000x1(TM), RM9000x2, RM9000x1GL(TM), RM9000x2GL and RM11200 highly integrated microprocessors visit www.pmc-sierra.com/processors.>