ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

Business Wire, April 4, 2005

SAN JOSE, Calif. -- ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) program to improve the complete design flow between Synopsys Design Compiler(R) FPGA (DC FPGA) Synthesis software, the VCS(R) comprehensive RTL verification solution and ProDesign CHIPit(R) ASIC Rapid Prototyping and Emulation systems. E[acute accent]"We are working with Synopsys to optimize a unified ASIC Rapid Prototyping flow that maximizes the productivity of our mutual customers," said Joseph Rothman, head of U.S. operations for ProDesign. "By integrating with industry standard Synopsys DC FPGA and the VCS complete RTL verification solution, we offer customers significant benefits when they use our solution for fast prototyping. Using DC FPGA software in the CHIPit verification flow, our customers have seen tremendous reductions in the risk and time required to prototype and verify their ASIC designs." E[acute accent]"ProDesign augments the Synopsys implementation solutions with a hardware-assist verification solution," said Karen Bartleson, director of Interoperability at Synopsys, Inc. "Together, Synopsys and ProDesign will cooperate to provide our mutual customers with the best quality of results in the shortest time possible as they prototype their complex SoCs. Additionally, it will allow our mutual customers to do real time early system software debug and check overall functionality, before committing to production ASIC. We are developing this solution with ProDesign and its CHIPit Rapid Prototyping and Emulation system through our in-Sync program, and are looking forward to a productive relationship with ProDesign." E[acute accent]The ProDesign CHIPit platforms can handle capacities up to 10 million ASIC gates and run at system speeds of up to 200MHz. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early "quasi prototyping" for firmware and software development.

E[acute accent]About the Synopsys in-Sync Program

E[acute accent]Synopsys' in-Sync program establishes relationships with EDA vendors to enable customer design flows to run as smoothly as possible as well as identifies optimal joint flows that maximize the productivity of EDA vendors' mutual customers. In-Sync certifies that the joint flows work and provides support to Synopsys' EDA partners. In-Sync is the primary point of contact for questions and technical information regarding Synopsys joint solutions and EDA tool interoperability. For more information, visit www.synopsys.com/partners/insync.> E[acute accent]About ProDesign

E[acute accent]ProDesign USA is dedicated to the sales and support of the complete family of CHIPit hardware-assisted verification platforms for ASIC and SoC developers in North America. The parent company, ProDesign Electronics Corporation, has headquarters in Munich, Germany. The privately held company was founded in 1981 and has over 80 employees, with facilities for research, design, and sales in Germany, France and the U.S. The company's products and services include the CHIPit family of hardware-assisted verification tools, hardware and software development, and image processing solutions. For more information, visit www.uchipit.com.

E[acute accent]ProDesign and CHIPit are registered trademarks of ProDesign Electronics Corporation. Synopsys, Design Compiler, VCS, and in-Sync are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.