Rambus to Showcase Its Chip Interface Technology and Partner Solutions at DesignCon 2005

Business Wire, Jan 31, 2005

A[paragraph]   Who:        Rambus Inc. (Nasdaq:RMBS)

A[paragraph]   Where:      DesignCon 2005
A[paragraph]               Booth # 205
A[paragraph]               Santa Clara Convention Center
A[paragraph]               Santa Clara, CA. USA

A[paragraph]   When:       February 1-3, 2005

A[paragraph]   Rambus will present the following papers during DesignCon's
    technical sessions:

A[paragraph]   --  Comparison of Adaptive and Non-adaptive Equalization
        Techniques in High Performance Backplanes Over Temperature,
        Humidity, and Impedance Variations;
        Tuesday, February 1, 2:50 pm - 3:30 pm
A[paragraph]   --  Modeling and Correlation of Supply Noise for a 3.2GHz
        Bidirectional Differential Memory Bus;
        Tuesday, February 1, 2:50 pm - 3:30 pm
A[paragraph]   --  Impact of Manufacturing Parametric Variations on Backplane
        System Performance;
        Wednesday, February 2, 9:40 am - 10:20 am

A[paragraph]   Abstracts for the presentations are available for download from
    the DesignCon 2005 conference catalog at
    www.designcon.com/pdf/dc05_catalog.pdf.

A[paragraph]   Also, Rambus will be showcasing its interface products, featuring
    demos on:

A[paragraph]   --  Serial backplane at 10 Gbps over standard ATCA (Advanced
        Telecom Compute Architecture);
A[paragraph]   --  PCI Express(TM) test platform showing a Rambus PCI Express PHY
        testchip passing PCI Express electrical compliance tests;
A[paragraph]   --  XDR(TM), a differential memory technology with data rates
        ranging from 3.2-8.0 GHz;
A[paragraph]   --  DDR, performing reads/writes with a GDDR1 device at 800Mbps
        (400MHz clock) speeds;
A[paragraph]   --  RDRAM(R), a high-volume technology with data rates up to
        1600MHz

A[paragraph]   Additionally, Rambus will feature partner solutions, including:

A[paragraph]   --  Cadence -- A vertical solution for PCI Express combining
        digital controller IP from Cadence, PHY IP from Rambus, and
        Verification IP from Denali;
A[paragraph]   --  Teradyne -- 2-PAM/4-PAM (Pulse Amplitude Modulation) signaling
        running at 1-10Gbps over a Teradyne connector;
A[paragraph]   --  Wavecrest -- A Rambus Fibre Channel-based testchip running at
        4.25Gbps, using a Wavecrest SIA-3600 instrument for jitter
        measurement