Cadence Encounter Platform Speeds Volume Production for STMicroelectronics' HDTV Decoder; Encounter Digital IC Design Platform Reduces Time to Volume for Single-Chip, Multi-Standard Set Top Box SoC

Business Wire, Feb 22, 2006

SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that the Cadence(R) Encounter(R) digital IC design platform has helped STMicroelectronics (ST) develop its first single-chip, multi-standard HDTV decoder. The Encounter platform's speed and capacity helped STMicroelectronics combine all set top box (STB) functions and multi-standard decoding circuitry onto a single chip in record time. E[acute accent]STMicroelectronics used the Cadence SoC Encounter(TM) RTL-to-GDSII System to help reduce end-product cost by eliminating an add-on co-processor for an existing product. The SoC Encounter system -- a configuration of the Encounter platform -- was used to develop the STB7100 chip with 90-nanometer process technology. It enabled the most cost-efficient solution for the product, targeted at the top end of the STB market. E[acute accent]"Our goal for STB7100 was to go into volume production as quickly as possible using the most cost-efficient solution to minimize both design and production costs for our end customers," said Christos Lagomichos, corporate vice president and Home Entertainment Group general manager. "This required an extraordinary level of integration to combine all the STB functions and multi-standard decoding circuitry onto a single chip using 90 nanometer process technology. SoC Encounter's advanced capabilities were key to our ability to design STB7100 in record time, and indispensable to achieve our goal of volume production of the most-cost efficient design." E[acute accent]To achieve the yield, die size, power, frequency, and density targets for the design, ST Microelectronics tapped the strength of the SoC Encounter system, including global synthesis, prototyping, placement, optimization, and routing. Advanced capabilities in multi-objective low-power synthesis, global physical synthesis, clock-tree synthesis, manufacturing-aware routing and extraction, and signal and power integrity analysis specifically address the complex issues of 90-nanometer design. E[acute accent]"We are extremely happy that the SoC Encounter system enabled this important customer to be the first to achieve this kind of success in the STB market," said Wei-Jin Dai, corporate vice president, R&D for Cadence. "The SoC Encounter system's strength is speed and capacity, and its ability to support complex, high-performance designs. We are particularly proud to be a part of development of this complex STB7100 product. We look forward to our continued relationship with ST."

E[acute accent]About Cadence

E[acute accent]Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

E[acute accent]Cadence, the Cadence logo and Encounter are registered trademarks of Cadence Design Systems, Inc., and SoC Encounter is a registered trademark of Cadence. All other trademarks are the property of their respective owners.